IP Library › Granted Patent US 8,995,176

Granted Patent B2

US 8,995,176 · App. 13/789,090 · Granted Mar 31, 2015

Dual-port SRAM systems

Inventor: Jhon Jhy Liaw (Zhudong Township, TW)

Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.

G11C11/412

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Quick Facts

Patent No.: US 8,995,176
App. No.: 13/789,090
Granted: Mar 31, 2015
Kind: B2

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Abstract

Schematic circuit designs for a dual-port SRAM cell are disclosed, together with various layout schemes for the dual-port SRAM cell. The dual-port SRAM cell comprises a storage unit and a plurality of partial dummy transistors connected to the outputs of the storage unit. Various layout schemes for the dual-port SRAM cell are further disclosed. A gate electrode serves as the gate for a pull-down transistor and a pull-up transistor, a gate of a first partial dummy transistor, and a gate of a second partial dummy transistor. A butt contact connects a long contact to the gate electrode. The long contact further connects to a drain of a pull-down transistor, a drain of a pull-up transistor, a drain of a first pass gate, and a drain of a second pass gate, wherein the first pass gate and the second pass gate share an active region.

Claims (75)

1. A device comprising:

a data latch storage unit comprising a first inverter having a first output and a first input, and a second inverter having a second output directly coupled to the first input, and a second input directly coupled to the first output, the second output being a complement of the first output;

a first dummy circuit comprising a first plurality of dummy transistors connected to the first output; and

a second dummy circuit comprising a second plurality of dummy transistors connected to the second output, wherein a respective one of the first plurality of dummy transistors and the second plurality of dummy transistors is formed in a respective active area of a substrate, and wherein an edge of the respective active area does not extend beyond a width of a gate electrode of the respective one of the first plurality of dummy transistors and the second plurality of dummy transistors.

2. The device of claim 1 , wherein:

the first plurality of dummy transistors of the first dummy circuit comprises:

a first partial dummy transistor having a first dummy drain and a first dummy gate, both the first dummy drain and the first dummy gate connected to the first output; and

a second partial dummy transistor comprising a second dummy drain and a second dummy gate, both the second dummy drain and the second dummy gate connected to the first output; and

the second plurality of dummy transistors of the second dummy circuit comprises:

a third partial dummy transistor having a third dummy drain and a third dummy gate, both the third dummy drain and the third dummy gate connected to the second output; and

a fourth partial dummy transistor comprising a fourth dummy drain and a fourth dummy gate, both the fourth dummy drain and the fourth dummy gate connected to the second output.

3. The device of claim 2 , wherein:

the first partial dummy transistor has a floating first dummy source;

the second partial dummy transistor has a floating second dummy source;

the third partial dummy transistor has a floating first dummy source; and

the fourth partial dummy transistor has a floating first dummy source.

4. The device of claim 1 , wherein:

the first inverter comprises a first pull-down transistor and a first pull-up transistor;

the second inverter comprises a second pull-down transistor and a second pull-up transistor; wherein:

a source of the first pull-down transistor and a source of the second pull-down transistor are connected a ground signal;

a source of the first pull-up transistor and a source of the second pull-up transistor are connected a voltage supply signal Vdd;

a gate of the first pull-down transistor, a gate of the first pull-up transistor, a drain of the second pull-down transistor, and a drain of the second pull-up transistor are connected to the first output; and

a gate of the second pull-down transistor, a gate of the second pull-up transistor, a drain of the first pull-down transistor, and a drain of the first pull-up transistor are connected to the second output.

5. The device of claim 1 , further comprising:

a first pass gate transistor with a drain connected to the first output, a gate connected to a first word line, and a source to a first bit line;

a second pass gate transistor with a drain connected to the first output, a gate connected to a second word line, and a source connected to a second bit line;

a third pass gate transistor with a drain connected to the second output, a gate connected to the first word line, and a source connected to a first complement bit line; and

a fourth pass gate transistor with a drain connected to the second output, a gate connected to the second word line, and a source connected to a second complement bit line.

6. A layout device comprising:

a first pull-down transistor and a fourth partial dummy transistor, wherein a first active area acts as a drain of the first pull-down transistor and a dummy drain of the fourth partial dummy transistor;

a first pull-up transistor and a third partial dummy transistor, wherein a second active area acts as a drain of the first pull-up transistor and a dummy drain of the third partial dummy transistor;

a second pull-down transistor and a first partial dummy transistor, wherein a third active area acts as a drain of the second pull-down transistor and a dummy drain of the first partial dummy transistor;

a second pull-up transistor and a second partial dummy transistor, wherein a fourth active area acts as a drain of the second pull-up transistor and a dummy drain of the second partial dummy transistor;

a ground signal connected to a source of the first pull-down transistor and a source of the second pull-down transistor; and

a voltage supply signal Vdd connected to a source of the first pull-up transistor and a source of the second pull-up transistor.

7. The device of claim 6 , further comprising:

a first gate electrode acting as a gate for the first pull-down transistor, a gate for the first pull-up transistor, a dummy gate for the first partial dummy transistor, and a dummy gate for the second partial dummy transistor; and

a second gate electrode acting as a gate for the second pull-down transistor, a gate for the second pull-up transistor, a dummy gate for the third partial dummy transistor, and a dummy gate for the fourth partial dummy transistor.

8. The device of claim 6 , wherein:

the first partial dummy transistor has a floating first dummy source;

the second partial dummy transistor has a floating second dummy source;

the third partial dummy transistor has a floating first dummy source; and

the fourth partial dummy transistor has a floating first dummy source.

9. The device of claim 7 , further comprising:

a first long contact connected to the first gate electrode by a first butt-contact, the first long contact further connected to the drain of the second pull-up transistor, the drain of the second pull-down transistor, the dummy drain of the first partial dummy transistor, and the dummy drain of the second partial dummy transistor.

10. The device of claim 9 , further comprising:

a second long contact connected to the second gate electrode by a second butt-contact, the second long contact further connected to the drain of the first pull-up transistor, the drain of the first pull-down transistor, the dummy drain of the third partial dummy transistor, and the dummy drain of the fourth partial dummy transistor.

11. The device of claim 10 , further comprising:

a first pass gate transistor and a second pass gate transistor, wherein the first pass gate transistor and the second pass gate transistor share a common drain area connected to the first long contact, a source of the first pass gate transistor is connected to a first bit line, a gate of the first pass gate transistor is connected to a first word line, a source of the second pass gate transistor is connected to a second bit line, a gate of the second pass gate transistor is connected to a second word line; and

a third pass gate transistor and a fourth pass gate transistor, wherein the third pass gate transistor and the fourth pass gate transistor share a common drain area connected to the second long contact, a source of the third pass gate transistor is connected to a first complement bit line, a gate of the third pass gate transistor is connected to the first word line, a source of the fourth pass gate transistor is connected to a second complement bit line, and a gate of the fourth pass gate transistor connected to the second word line.

12. The device of claim 11 , wherein the first pass gate transistor, the second pass gate transistor, the third pass gate transistor, and the fourth pass gate transistor are n-type FinFET transistors, each FinFET transistor comprising a plurality of fins.

13. The device of claim 11 , further comprising:

a first shielding line separating the first bit line and the second bit line; and

a second shielding line separating the first complement bit line and the second complement bit line;

wherein the first shielding line and the second shielding line are electrically connected to a constant voltage.

14. The device of claim 11 , wherein a first contact to the gate of the first pass gate transistor is diagonally opposite to a second contact to the gate of the second pass gate transistor, forming a zigzag style.

15. A layout device, comprising:

a first active area comprising a source of a first pull-down transistor at a first side of a first gate electrode, a drain of the first pull-down transistor at a second side of the first gate electrode, and a dummy drain for a fourth partial dummy transistor at a first side of a second gate electrode;

a second active area comprising a source of a first pull-up transistor at the first side of the first gate electrode, a drain of the first pull-up transistor at the second side of the first gate electrode, and a dummy drain for a third partial dummy transistor at the first side of the second gate electrode;

a third active area comprising a source of a second pull-down transistor at a second side of the second gate electrode, a drain of the second pull-down transistor at the first side of the second gate electrode, and a dummy drain for a first partial dummy transistor at the second side of the first gate electrode;

a fourth active area comprising a source of a second pull-up transistor at the second side of the second gate electrode, a drain of the second pull-up transistor at the first side of the second gate electrode, and a dummy drain for a second partial dummy transistor at the second side of the first gate electrode;

a first long contact connected to the first gate electrode by a first butt-contact, the drain of the second pull-up transistor, the drain of the second pull-down transistor, the drain of the first partial dummy transistor, and the drain of the second partial dummy transistor;

a second long contact connected to the second gate electrode by a second butt-contact, the drain of the first pull-up transistor, the drain of the first pull-down transistor, the drain of the third partial dummy transistor, and the drain of the fourth partial dummy transistor;

a ground signal connected to the source of the first pull-down transistor and the source of the second pull-down transistor; and

a voltage supply signal Vdd connected to the source of the first pull-up transistor and the source of the second pull-up transistor.

16. The device of claim 15 , further comprising:

a fifth active area comprising a first pass gate and a second pass gate, wherein the first pass gate and the second pass gate share a common drain area, a source of the first pass gate is connected to a first bit line, a gate of the first pass gate is connected to a first word line, a source of the second pass gate is connected to a second bit line, a gate of the second pass gate is connected to a second word line; and

a sixth active area comprising a third pass gate and a fourth pass gate, wherein the third pass gate and the fourth pass gate share a common drain area, a source of the third pass gate is connected to a first complement bit line, a gate of the third pass gate is connected to the first word line, a source of the fourth pass gate is connected to a second complement bit line, and a gate of the fourth pass gate connected to the second word line.

17. The device of claim 15 , wherein the first pull-up transistor and the second pull-up transistor are a p-type transistor formed within an n-type well.

18. The device of claim 16 , wherein the first pass gate transistor, the second pass gate transistor, the third pass gate transistor, and the fourth pass gate transistor are n-type FinFET transistors, each FinFET transistor comprising a plurality of fin-shape lines.

19. The device of claim 16 , further comprising:

a first shielding line separating the first bit line and the second bit line; and

a second shielding line separating the first complement bit line and the second complement bit line;

wherein the first shielding line and the second shielding line are electrically connected to a constant voltage.

20. The device of claim 16 , wherein a first contact to the gate of the first pass gate transistor is diagonally opposite to a second contact to the gate of the second pass gate transistor, forming a zigzag style.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 22, 2015

From: LIAW, JHON JHY

To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Reel/Frame 034789/0781 →

Continuity (1)

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