Nonvolatile memory device with upper source plane and buried bit line

1. A nonvolatile memory device comprising:

a channel layer extending in a vertical direction from a substrate;

a plurality of interlayer dielectric layers and word lines alternately stacked along the channel layer over the substrate;

a bit line formed under a plurality of interlayer dielectric layers and word lines, coupled to the channel layer, and extending in a direction crossing the word lines; and

a common source layer coupled to the channel layer and formed over the plurality of interlayer dielectric layers and word lines,

wherein the common source layer is divided into unit blocks by slits which are filled with an insulation layer.

2. The nonvolatile memory device of claim 1 , further comprising an interlayer dielectric layer and an upper select line interposed between the word lines and the common source layer.

3. The nonvolatile memory device of claim 1 , further comprising an interlayer dielectric layer and a lower select line interposed between the word lines and the bit line.

4. The nonvolatile memory device of claim 1 , further comprising a memory layer interposed between the channel layer and the word lines.

5. The nonvolatile memory device of claim 1 , further comprising a bit line contact plug coupled to the bit line and extending in the same direction as the channel layer.

6. The nonvolatile memory device of claim 1 , wherein the bit line includes polysilicon or metal silicide.

7. The nonvolatile memory device of claim 1 , wherein the common source layer includes a metal.

8. The nonvolatile memory device of claim 1 , wherein the common source layer has a plate or mesh shape.