Semiconductor device and driving method thereof
View Patent ↗In a memory module including a memory cell array including memory cells arranged in matrix, each including a first transistor using an oxide semiconductor and a first capacitor; a reference cell including a p-channel third transistor, a second capacitor, and a second transistor using an oxide semiconductor; and a refresh timing detection circuit including a resistor and a comparator, wherein when a potential is supplied to the first capacitor through the first transistor, a potential is supplied to the second capacitor through the second transistor, wherein a drain current value of the third transistor is changed in accordance with the potential stored in the second capacitor, and wherein when the drain current value of the third transistor is higher than a given value, a refresh operation of the memory cell array and the reference cell are performed.
1. A semiconductor device comprising:
a memory cell array including memory cells arranged in matrix; and
a refresh timing detection circuit operationally connected to the memory cell array, the refresh timing detection circuit including a reference cell and a comparator,
wherein each of the memory cells includes a first transistor including a first oxide semiconductor and a first capacitor electrically connected to the first transistor,
wherein the reference cell includes a second transistor including a second oxide semiconductor, a second capacitor electrically connected to the second transistor, and a third transistor electrically connected to the second capacitor, and
wherein the reference cell is electrically connected to the comparator.
2. The semiconductor device according to claim 1 ,
wherein the refresh timing detection circuit comprises a resistor, a reference word line and a reference bit line,
wherein a source of the second transistor is electrically connected to the reference bit line and a gate of the second transistor is electrically connected to the reference word line, and
wherein an electrode of the second capacitor is electrically connected to an electrode of the resistor and an electrode of the comparator.
3. The semiconductor device according to claim 1 ,
wherein the memory cell array comprises a word line and a bit line,
wherein a source of the first transistor is electrically connected to the bit line, and a gate of the first transistor is electrically connected to the word line, and
wherein a drain of the first transistor is electrically connected to an electrode of the first capacitor.
4. The semiconductor device according to claim 1 , wherein a gate of the first transistor is electrically connected to a gate of the second transistor.
5. The semiconductor device according to claim 2 ,
wherein the reference bit line is connected to a bit line, and
wherein the reference word line is connected to a word line.
6. The semiconductor device according to claim 1 , wherein the first transistor and the second transistor have a same structure.
7. The semiconductor device according to claim 1 , wherein a capacitance of the second capacitor is smaller than a capacitance of the first capacitor.
8. The semiconductor device according to claim 1 , wherein each of the first oxide semiconductor and the second oxide semiconductor comprises at least one of indium and zinc.
9. A semiconductor device comprising:
a memory cell array including memory cells arranged in matrix; and
a refresh timing detection circuit operationally connected to the memory cell array, the refresh timing detection circuit including a reference cell and a comparator,
wherein each of the memory cells includes a first transistor including a first oxide semiconductor and a first capacitor electrically connected to the first transistor,
wherein the reference cell includes a second transistor including a second oxide semiconductor, a second capacitor electrically connected to the second transistor, and a third transistor including a p-type channel electrically connected to the second capacitor, and
wherein the reference cell is electrically connected to the comparator.
10. The semiconductor device according to claim 9 ,
wherein the refresh timing detection circuit comprises a resistor, a reference word line and a reference bit line,
wherein a gate of the third transistor is electrically connected to a drain of the second transistor and an electrode of the second capacitor,
wherein a source of the second transistor is electrically connected to the reference bit line and a gate of the second transistor is electrically connected to the reference word line, and
wherein a drain of the third transistor is electrically connected to an electrode of the resistor and an electrode of the comparator.
11. The semiconductor device according to claim 9 ,
wherein the memory cell array comprises a word line and a bit line,
wherein a source of the first transistor is electrically connected to the bit line, and a gate of the first transistor is electrically connected to the word line, and
wherein a drain of the first transistor is electrically connected to an electrode of the first capacitor.
12. The semiconductor device according to claim 9 , wherein a gate of the first transistor is electrically connected to a gate of the second transistor.
13. The semiconductor device according to claim 10 ,
wherein the reference bit line is connected to a bit line, and
wherein the reference word line is connected to a word line.
14. The semiconductor device according to claim 9 , wherein the first transistor and the second transistor have a same structure.
15. The semiconductor device according to claim 9 , wherein a capacitance of the second capacitor is smaller than a capacitance of the first capacitor.
16. The semiconductor device according to claim 9 , wherein each of the first oxide semiconductor and the second oxide semiconductor comprises at least one of indium and zinc.
17. A semiconductor device comprising:
a memory cell array including memory cells arranged in matrix; and
a refresh timing detection circuit operationally connected to the memory cell array, the refresh timing detection circuit including reference cells and a comparator,
wherein each of the memory cells includes a first transistor including a first oxide semiconductor and a first capacitor electrically connected to the first transistor,
wherein each of the reference cells includes a second transistor including a second oxide semiconductor, a second capacitor electrically connected to the second transistor, and a third transistor electrically connected to the second capacitor, and
wherein the comparator is electrically connected to at least one of the reference cells.
18. The semiconductor device according to claim 17 ,
wherein the refresh timing detection circuit comprises a resistor, a reference word line and a reference bit line,
wherein a source of the second transistor is electrically connected to the reference bit line and a gate of the second transistor is electrically connected to the reference word line, and
wherein an electrode of the second capacitor is electrically connected to an electrode of the resistor and an electrode of the comparator.
19. The semiconductor device according to claim 17 ,
wherein the memory cell array comprises a word line and a bit line,
wherein a source of the first transistor is electrically connected to the bit line and a gate of the first transistor is electrically connected to the word line, and
wherein a drain of the first transistor is electrically connected to an electrode of the first capacitor.
20. The semiconductor device according to claim 17 , wherein a gate of the first transistor is electrically connected to a gate of the second transistor.
21. The semiconductor device according to claim 18 ,
wherein the reference bit line is connected to a bit line, and
wherein the reference word line is connected to a word line.
22. The semiconductor device according to claim 17 , wherein the first transistor and the second transistor have a same structure.
23. The semiconductor device according to claim 17 , wherein a capacitance of the second capacitor is smaller than a capacitance of the first capacitor.
24. The semiconductor device according to claim 17 , wherein each of the first oxide semiconductor and the second oxide semiconductor comprises at least one of indium and zinc.
25. The semiconductor device according to claim 17 , wherein the third transistor includes a p-type channel.