IP Library Granted Patent US 9,006,092
Granted Patent B2
US 9,006,092 · App. 13/288,041 · Granted Apr 14, 2015

Semiconductor structure having fluoride metal layer and process thereof

Inventors: Kun-Hsien Lin (Hsinchu, TW); Chun-Hsien Lin (Tainan, TW); Hsin-Fu Huang (Tainan, TW)
Assignee: United Microelectronics Corp.
H01L21/823842H01L21/265H01L21/28088H01L29/4966H01L29/513H01L29/517H01L29/66545
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,006,092
App. No.
13/288,041
Granted
Apr 14, 2015
Kind
B2
Abstract

A semiconductor structure includes a substrate, a dielectric layer and a fluoride metal layer. The dielectric layer is located on the substrate. The fluoride metal layer is located on the dielectric layer. Furthermore, the present invention also provides a semiconductor process to form said semiconductor structure.

Claims (27)

1. A semiconductor structure, comprising:

a substrate;

a dielectric layer located on the substrate;

a fluoride metal layer located on the dielectric layer; and

a fluoride metal gate layer located on and directly contacting the fluoride metal layer.

2. The semiconductor structure according to claim 1 , wherein the dielectric layer comprises a dielectric layer having a high dielectric constant.

3. The semiconductor structure according to claim 2 , wherein the dielectric layer having a high dielectric constant further comprises a hafnium oxide (HfO2) layer.

4. The semiconductor structure according to claim 1 , wherein the dielectric layer having a high dielectric constant comprises a fluoride dielectric layer having a high dielectric constant.

5. The semiconductor structure according to claim 1 , wherein the fluoride metal layer comprises a fluoride work function metal layer.

6. The semiconductor structure according to claim 1 , wherein the fluoride metal layer comprises a fluoride titanium nitride layer.

7. The semiconductor structure according to claim 1 , wherein a work function value of the semiconductor structure is between 4.9 eV and 5.1 eV.

8. The semiconductor structure according to claim 1 , wherein the semiconductor structure comprises a PMOS transistor.

9. A semiconductor process, comprising:

providing a substrate;

forming a dielectric layer on the substrate;

forming a fluoride metal layer on the dielectric layer, wherein the fluoride metal layer is formed by an atomic layer deposition (ALD) process with a precursor of fluoride comprising titanium tetrafluoride (TiF4); and

forming a fluoride metal gate layer directly on the fluoride metal layer.

10. The semiconductor process according to claim 9 , wherein the dielectric layer comprises a dielectric layer having a high dielectric constant.

11. The semiconductor process according to claim 9 , wherein the fluoride metal layer comprises a fluoride work function metal layer.

12. The semiconductor process according to claim 9 , wherein the fluoride metal layer comprises a fluoride titanium nitride layer.

13. The semiconductor process according to claim 9 , wherein forming the fluoride metal layer comprises:

forming a metal layer on the dielectric layer; and

doping the metal layer with fluoride ions to form the fluoride metal layer.

14. The semiconductor process according to claim 9 , wherein a barrier layer is formed on the dielectric layer after the dielectric layer is formed.

15. The semiconductor structure according to claim 1 , further comprising a barrier layer comprising a fluoride tantalum nitride layer located between the dielectric layer and the fluoride metal layer.

16. The semiconductor structure according to claim 1 , wherein the dielectric layer comprises a hafnium silicon oxynitride (HfSiON) layer.

17. The semiconductor structure according to claim 1 , wherein the fluoride metal layer has a U-shaped cross-sectional profile.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 3, 2011
From: LIN, KUN-HSIEN; LIN, CHUN-HSIEN; HUANG, HSIN-FU
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 027165/0784 →
Continuity (1)
Related Publication 20130113053A1 · May 9, 2013