IP Library Granted Patent US 9,006,787
Granted Patent B2
US 9,006,787 · App. 14/067,928 · Granted Apr 14, 2015

Semiconductor device including gate electrode provided over active region in p-type nitride semiconductor layer and method of manufacturing the same, and power supply apparatus

Inventor: Atsushi Yamada (Kawasaki, JP)
Assignee: Transphorm Japan, Inc.
H01L29/778H01L29/2003H01L29/42364H01L29/66462H01L29/7783H01L29/7787
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Quick Facts
Patent No.
US 9,006,787
App. No.
14/067,928
Granted
Apr 14, 2015
Kind
B2
Abstract

A semiconductor device includes a nitride semiconductor stacked structure including a carrier transit layer and a carrier supply layer; a p-type nitride semiconductor layer provided over the nitride semiconductor stacked structure and including an active region and an inactive region; an n-type nitride semiconductor layer provided on the inactive region in the p-type nitride semiconductor layer; and a gate electrode provided over the active region in the p-type nitride semiconductor layer.

Claims (44)

1. A semiconductor device comprising:

a nitride semiconductor stacked structure comprising a carrier transit layer and a carrier supply layer;

a p-type nitride semiconductor layer provided over the nitride semiconductor stacked structure and comprising an active region and an inactive region;

an n-type nitride semiconductor layer provided on the inactive region in the p-type nitride semiconductor layer; and

a gate electrode provided over the active region in the p-type nitride semiconductor layer;

wherein

the n-type nitride semiconductor layer is depleted, causing it to have fixed positive charges, and the fixed positive charges in the n-type nitride semiconductor layer cause a conduction band energy level at an interface between the carrier transit layer and the carrier supply layer to be comparable to that in a similar structure which lacks the p-type nitride semiconductor layer and the n-type nitride semiconductor layer.

2. The semiconductor device according to claim 1 , wherein the active region is a region having a fixed charge, and the inactive region is a region without a fixed charge.

3. The semiconductor device according to claim 1 , wherein the p-type nitride semiconductor layer and the n-type nitride semiconductor layer include a same nitride semiconductor material.

4. The semiconductor device according to claim 1 , wherein the p-type nitride semiconductor layer includes a GaN, AlN or InN crystal, or a mixed crystal thereof, and the n-type nitride semiconductor layer includes a GaN, AlN or InN crystal, or a mixed crystal thereof.

5. The semiconductor device according to claim 1 , wherein the p-type nitride semiconductor layer is a p-type GaN layer, and the n-type nitride semiconductor layer is an n-type GaN layer.

6. The semiconductor device according to claim 1 , wherein the active region in the p-type nitride semiconductor layer and the gate electrode Schottky-contact.

7. The semiconductor device according to claim 1 , further comprising a gate insulation film between the active region in the p-type nitride semiconductor layer and the gate electrode.

8. The semiconductor device according to claim 1 , wherein the nitride semiconductor stacked structure includes a GaN, AlN or InN crystal, or a mixed crystal thereof.

9. A semiconductor device comprising:

a stage mounting a semiconductor chip comprising: a nitride semiconductor stacked structure comprising a carrier transit layer and a carrier supply layer; a p-type nitride semiconductor layer provided over the nitride semiconductor stacked structure and comprising an active region and an inactive region; an n-type nitride semiconductor layer provided on the inactive region in the p-type nitride semiconductor layer; and a gate electrode provided over the active region in the p-type nitride semiconductor layer;

a gate lead connected to the gate pad in the semiconductor chip;

a source lead connected to the source pad in the semiconductor chip;

a drain lead connected to the drain pad in the semiconductor chip; and

an encapsulation resin;

wherein

the n-type nitride semiconductor layer is depleted, causing it to have fixed positive charges, and the fixed positive charges in the n-type nitride semiconductor layer cause a conduction band energy level at an interface between the carrier transit layer and the carrier supply layer to be comparable to that in a similar structure which lacks the p-type nitride semiconductor layer and the n-type nitride semiconductor layer.

10. The semiconductor device according to claim 9 , wherein the active region is a region having a fixed charge, and the inactive region is a region without a fixed charge.

11. The semiconductor device according to claim 9 , wherein the p-type nitride semiconductor layer and the n-type nitride semiconductor layer include a same nitride semiconductor material.

12. The semiconductor device according to claim 9 , wherein the p-type nitride semiconductor layer includes a GaN, AlN or InN crystal, or a mixed crystal thereof, and the n-type nitride semiconductor layer includes a GaN, AlN or InN crystal, or a mixed crystal thereof.

13. The semiconductor device according to claim 9 , wherein the p-type nitride semiconductor layer is a p-type GaN layer, and the n-type nitride semiconductor layer is an n-type GaN layer.

14. The semiconductor device according to claim 9 , wherein the active region in the p-type nitride semiconductor layer and the gate electrode Schottky-contact.

15. The semiconductor device according to claim 9 , further comprising a gate insulation film between the active region in the p-type nitride semiconductor layer and the gate electrode.

16. The semiconductor device according to claim 9 , wherein the nitride semiconductor stacked structure includes a GaN, AlN or InN crystal, or a mixed crystal thereof.

17. A power supply apparatus comprising:

a semiconductor device comprising:

a nitride semiconductor stacked structure comprising a carrier transit layer and a carrier supply layer;

a p-type nitride semiconductor layer provided over the nitride semiconductor stacked structure and comprising an active region and an inactive region;

an n-type nitride semiconductor layer provided on the inactive region in the p-type nitride semiconductor layer; and

a gate electrode provided over the active region in the p-type nitride semiconductor layer;

wherein

the n-type nitride semiconductor layer is depleted, causing it to have fixed positive charges, and the fixed positive charges in the n-type nitride semiconductor layer cause a conduction band energy level at an interface between the carrier transit layer and the carrier supply layer to be comparable to that in a similar structure which lacks the p-type nitride semiconductor layer and the n-type nitride semiconductor layer.

18. The semiconductor device according to claim 17 , wherein the active region is a region having a fixed charge, and the inactive region is a region without a fixed charge.

19. The semiconductor device according to claim 17 , wherein the p-type nitride semiconductor layer and the n-type nitride semiconductor layer include a same nitride semiconductor material.

20. The semiconductor device according to claim 17 , wherein the p-type nitride semiconductor layer includes a GaN, AlN or InN crystal, or a mixed crystal thereof, and the n-type nitride semiconductor layer includes a GaN, AlN or InN crystal, or a mixed crystal thereof.

21. The semiconductor device according to claim 17 , wherein the p-type nitride semiconductor layer is a p-type GaN layer, and the n-type nitride semiconductor layer is an n-type GaN layer.

22. The semiconductor device according to claim 17 , wherein the active region in the p-type nitride semiconductor layer and the gate electrode Schottky-contact.

23. The semiconductor device according to claim 17 , further comprising a gate insulation film between the active region in the p-type nitride semiconductor layer and the gate electrode.

24. The semiconductor device according to claim 17 , wherein the nitride semiconductor stacked structure includes a GaN, AN or InN crystal, or a mixed crystal thereof.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 8, 2014
From: YAMADA, ATSUSHI
To: FUJITSU LIMITED
Reel/Frame 033499/0949 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 9, 2014
From: FUJITSU LIMITED
To: TRANSPHORM JAPAN, INC.
Reel/Frame 032865/0196 →
Priority Claims (1)
JP 2011-032042 · Feb 17, 2011 · national
Continuity (2)
Division 13308686 · Dec 1, 2011
Related Publication 20140054606A1 · Feb 27, 2014