IP Library › Granted Patent US 9,012,266
Granted Patent B2
US 9,012,266 · App. 14/480,464 · Granted Apr 21, 2015

Copper post solder bumps on substrates

Inventors: Jae-Woong Nah (Armonk, NY); Da-Yuan Shih (Armonk, NY)
Assignee: International Business Machines Corporation
H01L24/81H01L24/11H01L21/563H01L2924/014H01L2224/11312H01L2224/1134H01L2224/81815H01L2224/81193H01L2224/81203H01L2924/01029H01L2924/01079H01L2924/01013
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Quick Facts
Patent No.
US 9,012,266
App. No.
14/480,464
Granted
Apr 21, 2015
Kind
B2
Abstract

A method comprises forming semiconductor flip chip interconnects having electrical connecting pads and electrically conductive posts terminating in distal ends operatively associated with the pads. We solder bump the distal ends by injection molding, mask the posts on the pads with a mask having a plurality of through hole reservoirs and align the reservoirs in the mask to be substantially concentric with the distal ends. Injecting liquid solder into the reservoirs and allowing it to cool provides solidified solder on the distal ends, which after mask removal produces a solder bumped substrate which we position on a wafer to leave a gap between the wafer and the substrate. The wafer has electrically conductive sites on the surface for soldering to the posts. Abutting the sites and the solder bumped posts followed by heating joins the wafer and substrate. The gap is optionally filled with a material comprising an underfill.

Claims (43)

1. In a method comprising forming a semiconductor flip chip from a wafer having solderable electrical conducting sites and a substrate having electrical connecting pads and electrically conductive posts operatively associated with said pads and extending away from said pads to terminate in distal ends, said wafer including UBM sites the steps comprising solder bumping said distal ends through openings in a solder mask by injection molding solder onto said distal ends to produce a solder bumped substrate and soldering said solder bumped substrate to said sites wherein said distal ends extend into said mask through said openings; and further comprising:

a. providing said substrate having said posts on said pads;

b. providing said mask wherein said openings comprise a plurality of through hole reservoirs and aligning said reservoirs in said mask to be substantially concentric with said distal ends;

c. injecting liquid solder into said reservoirs to provide a volume of liquid solder on said distal ends;

d. cooling said liquid solder in said reservoirs to solidify said solder;

e. removing said mask to expose said solidified solder after said cooling and thereby provide a solder bumped substrate;

f. positioning said solder bumped substrate on said wafer in a manner that leaves a gap between said wafer and said substrate;

g. filling said gap with a material comprising an underfill; and

h. abutting said posts and said sites and joining said wafer to said substrate by heating said solder to its liquidus temperature.

2. In a method comprising forming a semiconductor flip chip from a wafer having solderable electrical conducting sites comprising solder bumped sites on the surface of said wafer and a substrate having electrical connecting pads and electrically conductive posts operatively associated with said pads and extending away from said pads to terminate in distal ends, the steps comprising solder bumping said distal ends through openings in a solder mask by injection molding solder onto said distal ends to produce a solder bumped substrate and soldering said solder bumped substrate to said sites wherein said distal ends extend into said mask through said openings, wherein said openings in said mask comprise reservoirs for receiving molten solder, wherein said reservoir and said posts sealingly engage one another toward the proximal ends of said posts in a manner to substantially minimize or eliminate the leakage of molten solder from said reservoir.

3. The method of claim 2 wherein substantially all of said sites are solder bumped.

4. The method of claim 2 wherein the volume of solder in said solder bumped electrically conductive posts is sufficient to reduce the size and volume of the solder on said solder bumped sites.

5. In a method comprising forming a semiconductor flip chip from a wafer having solderable electrical conducting sites and a substrate having electrical connecting pads and electrically conductive posts operatively associated with said pads and extending away from said pads to terminate in distal ends, wherein said posts comprise metal posts selected from Cu, Au, Al and their alloys; the steps comprising solder bumping said distal ends through openings in a solder mask by injection molding solder onto said distal ends to produce a solder bumped substrate and soldering said solder bumped substrate to said sites wherein said distal ends extend into said mask through said openings; and further comprising:

a. providing said substrate having said posts on said pads;

b. providing said mask wherein said openings comprise a plurality of through hole reservoirs and aligning said reservoirs in said mask to be substantially concentric with said distal ends;

c. injecting liquid solder into said reservoirs to provide a volume of liquid solder on said distal ends;

d. cooling said liquid solder in said reservoirs to solidify said solder;

e. removing said mask to expose said solidified solder after said cooling and thereby provide a solder bumped substrate;

f. positioning said solder bumped substrate on said wafer in a manner that leaves a gap between said wafer and said substrate; and

g. abutting said posts and said sites and joining said wafer to said substrate by heating said solder to its liquidus temperature.

6. The method of claim 2 where the height of said posts is substantially the same as the thickness of said mask or less than the thickness of said mask.

7. The method of claim 2 wherein said posts are placed only on some of said pads and solder bumps placed on at least some of the other of said pads that do not have said posts in order to decrease any stress in said flip chip.

8. In a method comprising forming a semiconductor flip chip from a wafer having solderable electrical conducting sites on the surface of said wafer comprising solder bumped sites, and a substrate having electrical connecting pads and electrically conductive posts operatively associated with said pads and extending away from said pads to terminate in distal ends, the steps comprising solder bumping said distal ends through openings in a solder mask by injection molding solder onto said distal ends to produce a solder bumped substrate and soldering said solder bumped substrate to said sites wherein said distal ends extend into said mask through said openings; and further comprising:

a. providing said substrate having said posts on said pads;

b. providing said mask wherein said openings comprise a plurality of through hole reservoirs and aligning said reservoirs in said mask to be substantially concentric with said distal ends;

c. injecting liquid solder into said reservoirs to provide a volume of liquid solder on said distal ends;

d. cooling said liquid solder in said reservoirs to solidify said solder;

e. removing said mask to expose said solidified solder after said cooling and thereby provide a solder bumped substrate;

f. positioning said solder bumped substrate on said wafer in a manner that leaves a gap between said wafer and said substrate;

g. abutting said posts and said sites and joining said wafer to said substrate by heating said solder to its liquidus temperature.

9. The method of claim 2 wherein said conductive posts comprise stud bumps.

10. The method of claim 9 wherein said stud bumps comprise Cu, Au or Al stud bumps, mixtures thereof and alloys thereof.

11. The method of claim 8 wherein said conductive posts comprise stud bumps.

12. The method of claim 11 wherein said stud bumps comprise Cu, Au or Al stud bumps, mixtures thereof and alloys thereof.

13. The method of claim 2 wherein said wafer includes UBM sites.

14. The method of claim 13 wherein said UBM sites are operatively associated with an electrically conductive metal pedestal.

15. The method of claim 8 wherein said wafer includes UBM sites.

16. The method of claim 15 wherein said UBM sites are operatively associated with an electrically conductive metal pedestal.

17. The method of claim 2 wherein said distal ends only extend partially into said mask.

18. The method of claim 8 wherein said distal ends only extend partially into said mask.

19. The method of claim 2 wherein said electrically conductive posts taper inwardly toward said distal ends.

20. The method of claim 8 wherein said electrically conductive posts taper inwardly toward said distal ends.

21. The method of claim 8 wherein said reservoir and said posts sealingly engage one another toward the proximal ends of said post in a manner to substantially minimize or eliminate leakage of molten solder from said reservoir.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 25, 2014
From: NAH, JAE-WOONG; SHIH, DA-YUAN
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 033822/0122 →
Continuity (3)
Division 13078807 · Apr 1, 2011
Division 14016086 · Aug 31, 2013
Related Publication 20150031173A1 · Jan 29, 2015