Modulating germanium percentage in MOS devices
An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is overlying the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A metal silicide region is over and in contact with the second silicon germanium region.
1. An integrated circuit structure comprising:
a semiconductor substrate;
a gate stack over the semiconductor substrate;
an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack;
a first silicon germanium region in the opening, wherein the first silicon germanium region has a first germanium percentage;
a second silicon germanium region over the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage; and
a metal silicide region over and in contact with the second silicon germanium region, wherein the second silicon germanium region comprises an upper portion on a side of, and is level with, the metal silicide region.
2. The integrated circuit structure of claim 1 further comprising:
a silicon cap substantially free from germanium over the second silicon germanium region, wherein the metal silicide region penetrates through the silicon cap.
3. The integrated circuit structure of claim 2 , wherein the second silicon germanium region has a first thickness, and wherein the silicon cap has a second thickness greater than the first thickness.
4. The integrated circuit structure of claim 1 , wherein the second silicon germanium region comprises a lower portion, wherein a top surface of the lower portion is in contact with a bottom surface of the metal silicide region, and a bottom surface of the lower portion is in contact with a top surface of the first silicon germanium region.
5. The integrated circuit structure of claim 1 , wherein at an interface between the first silicon germanium region and the second silicon germanium region, germanium percentages change abruptly.
6. The integrated circuit structure of claim 1 , wherein the second germanium percentage is greater than the first germanium percentage by a difference greater than about 5 percent.
7. An integrated circuit structure comprising:
a semiconductor substrate;
a gate stack over the semiconductor substrate, wherein the gate stack is comprised in a Metal-Oxide-Semiconductor (MOS) device;
a source/drain region of the MOS device extending into the semiconductor substrate, wherein the source/drain region comprises:
a first silicon germanium region, wherein the first silicon germanium region has a first germanium percentage; and
a second silicon germanium region over the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage greater than the first germanium percentage;
a silicon cap over and contacting the second silicon germanium region; and
a metal silicide region penetrating through the silicon cap to contact the second silicon germanium region.
8. The integrated circuit structure of claim 7 , wherein the second germanium percentage is greater than the first germanium percentage by a difference greater than about 5 percent.
9. The integrated circuit structure of claim 7 , wherein the second silicon germanium region comprises a portion between, and in contact with, the first silicon germanium region and the metal silicide region.
10. The integrated circuit structure of claim 9 , wherein the portion of the second silicon germanium region is underlying the metal silicide region and overlying the first silicon germanium region.
11. The integrated circuit structure of claim 9 , wherein the second silicon germanium region further comprises an additional portion on a side of, and level with, the metal silicide region.
12. The integrated circuit structure of claim 7 , wherein an interface between the first silicon germanium region and the second silicon germanium region is higher than an interface between the semiconductor substrate and the gate stack.
13. The integrated circuit structure of claim 12 , wherein the first silicon germanium region comprises a top portion higher than the interface, and the second germanium percentage is higher than a germanium percentage of the top portion of the first silicon germanium region.
14. A method comprising:
forming a gate stack over a semiconductor substrate;
forming an opening extending into the semiconductor substrate, wherein the opening is on a side of the gate stack;
performing a first epitaxy to grow a first silicon germanium region in the opening, wherein a top portion of the first silicon germanium region is higher than an interface between a bottom surface of the gate stack and the semiconductor substrate, and wherein the top portion of the first silicon germanium region has a first germanium percentage;
performing a second epitaxy to grow a second silicon germanium region over the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage; and
forming silicon cap substantially free from germanium over and contacting the second silicon germanium region.
15. The method of claim 14 further comprising, after forming the silicon cap, performing a silicidation to silicide the silicon cap, wherein a metal silicide formed from the silicidation contacts a remaining portion of the second silicon germanium region.
16. The method of claim 15 , wherein after the silicidation, a bottom layer of the second silicon germanium region remains un-silicided, and a top layer of the second silicon germanium region is silicided.
17. The method of claim 14 , wherein no germanium is introduced into the silicon cap.
18. The method of claim 14 further comprising:
after forming the silicon cap, forming an Inter-Layer Dielectric (ILD) over the gate stack and the silicon cap;
forming a contact opening in the ILD, wherein the silicon cap is exposed to the contact opening;
after the contact opening is formed, performing a silicidation on the silicon cap; and
filling the contact opening with a conductive material.
19. The method of claim 14 , wherein the first silicon germanium region comprises a top surface having two slopes on opposite sides of a substantially flat top surface, and wherein the second silicon germanium region is formed on the substantially flat top surface and not on the two slopes.
20. The integrated circuit structure of claim 7 , wherein the first silicon germanium region comprises a top surface having two slopes on opposite sides of a substantially flat top surface, and wherein the second silicon germanium region is formed on the substantially flat top surface and not on the two slopes.
21. The integrated circuit structure of claim 1 , wherein a first interface between the first silicon germanium region and the second silicon germanium region is higher than a second interface between the semiconductor substrate and the gate stack, and a top portion of the first silicon germanium region higher than the second interface has the first germanium percentage.