Semiconductor device and method of manufacturing the same
View Patent ↗A semiconductor device includes a channel layer protruding from a substrate and having protrusions extending from a sidewall thereof. Floating gates surrounding the channel layer are provided between the protrusions. Control gates surrounding the floating gates are stacked along the channel layer. Interlayer insulating layers are interposed between the control gates stacked along the channel layer. A level difference exists between a lateral surface of each of the floating gates, and a lateral surface of each of the protrusions.
1. A semiconductor device, comprising:
a channel layer protruding from a substrate and having protrusions extending from a sidewall thereof and concaves provided between the protrusions;
floating gates surrounding the channel layer and disposed in the concaves to be separate from each other;
control gates surrounding the floating gates, respectively; and
interlayer insulating layers surrounding the protrusions and interposed between the control gates,
wherein a level difference exists between a lateral surface of each of the floating gates and a lateral surface of each of the protrusions.
2. The semiconductor device of claim 1 , wherein the lateral surface of each floating gate protrudes further than the lateral surface of each protrusion.
3. The semiconductor device of claim 1 , wherein the floating gates have different thicknesses from the control gates.
4. The semiconductor device of claim 1 , wherein the channel layer includes a single crystalline silicon layer, a polycrystalline polysilicon layer, an amorphous silicon layer, a single crystalline germanium layer, a polycrystalline polygermanium layer, an amorphous germanium layer, a single crystalline silicon germanium layer, a polycrystalline polysilicon germanium layer, an amorphous silicon germanium layer, a metal layer, a silicide layer, a carbon nanotube, graphene, or a combination thereof.
5. The semiconductor device of claim 1 , wherein the floating gates and the control gates each include a polycrystalline polysilicon layer, a metal layer, a silicide layer, a carbon tube, graphene, or a combination thereof.
6. The semiconductor device of claim 1 , further comprising voids provided between the protrusions and the interlayer insulating layers and provided between the floating gates.
7. The semiconductor device of claim 1 , further comprising voids provided in the interlayer insulating layers between the floating gates and further extending between the control gates.
8. The semiconductor device of claim 1 , wherein each protrusion includes a metal layer, or a polysilicon layer doped with impurities.
9. The semiconductor device of claim 1 , further comprising charge blocking layers interposed between the control gates and the floating gates and covering top and bottom surfaces of the control gates.
10. The semiconductor device of claim 1 , further comprising a tunnel insulating layer surrounding the channel layer.
11. The semiconductor device of claim 1 , wherein a length of each protrusion overlapping with each floating gate is between about 20 to 90% of a length of the floating gate.
12. The semiconductor device of claim 1 , wherein portions of corners of the floating gates have a radius of curvature ranging from between about 0.002 to 0.009 μm.
13. The semiconductor device of claim 1 , wherein each floating gate has a length of about 30 nm or less.