Clock drift compensation interpolator adjusting buffer read and write clocks
In at least some embodiments, an electronic device includes a data sink and a buffer coupled to the data sink. The buffer is configured to receive streaming data in transit to the data sink. The electronic device also includes a clock drift compensation controller coupled to the buffer, wherein the clock drift compensation controller is configured to apply either of two predetermined clock drift compensation values to a clock rate for the buffer whenever a buffer fullness status value is offset from a predetermined threshold.
1. A clock drift compensation interpolator comprising:
a buffer; and
control logic coupled to the buffer, the control logic being configured to apply a first clock drift compensation value to a clock rate for the buffer when a buffer fullness status value is above a threshold and to apply a second clock drift compensation value to the clock rate for the buffer when the buffer fullness status value is below the threshold, the control logic being configured to determine a difference between a read clock value and a write clock value for the buffer and to adjust the first and second clock drift compensation values based on the difference.
2. The clock drift compensation interpolator of claim 1 , wherein the control logic determines the buffer fullness status value and a rate of change for the buffer fullness status value based on monitoring a pointer location for the buffer.
3. The clock drift compensation interpolator of claim 1 , wherein the first clock drift compensation value is a positive drift compensation value and wherein the second clock drift compensation is a negative drift compensation value equal in magnitude to the positive drift compensation value, and wherein the control logic is configured to toggle application of the positive and negative drift compensation values to a write clock for the buffer.