Structure for asymmetrical performance multi-processors
A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design, for allocating processing functions between a primary processor and a secondary processor is disclosed. A primary processor is provided that performs routine processing duties, including execution of application program code, while the secondary processor is in a sleep state. When the load on the primary processor is deemed to be excessive, the secondary processor is awakened from a sleep state and assigned to perform processing functions that would otherwise need to be performed by the primary processor. If temperatures in the system rise above a threshold, the secondary processor is returned to the sleep state.
1. A design structure embodied in a non-transitory machine readable storage medium for at least one of designing, manufacturing, and testing a design, the design structure comprising:
a multi-processor system comprising:
a primary processor to perform processor functions exclusive of a secondary processor, the processor functions comprising application code execution, during non-detection of a special condition, and to place the second processor in a wake state in the event of detection of the special condition; and
the secondary processor to perform at least some processor functions when a special condition is detected and the secondary processor is in the wake state, wherein the secondary processor remains in a sleep state during non-detection of the special condition, wherein the secondary processor is returned to the sleep state from the wake state if a monitored temperature exceeds a threshold, and wherein the secondary processor is returned to the sleep state if usage of the primary processor falls below a threshold.
2. The design structure of claim 1 , wherein a common operating system is executed by both the primary processor and the secondary processor when the secondary processor is in operation to perform processor functions.
3. The design structure of claim 1 , wherein the primary processor configures the secondary processor.
4. The design structure of claim 1 , wherein the secondary processor executes application program code when not in the sleep state.
5. The design structure of claim 1 , wherein the primary processor executes a system idle task during non-detection of the special condition, and wherein the secondary processor executes the system idle task when the secondary processor is in the wake state.
6. The design structure of claim 1 , wherein the special condition occurs if usage of the primary processor exceeds a threshold.
7. The design structure of claim 1 , wherein the special condition occurs if a floating point instruction is received for execution by the primary processor.
8. The design structure of claim 1 , wherein the secondary processor is returned to the sleep state if thermal conditions exceed a threshold.
9. The design structure of claim 1 , further comprising a netlist that describes the multi-processor system.
10. The design structure of claim 1 , wherein the design structure resides on the non-transitory machine readable storage medium as a data format used for an exchange of layout data of integrated circuits.