Flash memory for code and data storage
A flash memory for code and data storage includes a code memory array having fast read access and suitability for execute in place, a data memory array having the characteristics of low bit cost and high density storage, and a suitable interface to provide access to both the code and data. The code memory array may be a NOR array or a performance-enhanced NAND array. The memory may be implemented in a single chip package or multi-chip package solution.
1. A flash memory comprising:
a first chip comprising:
a NOR flash memory array specialized for code storage; and
a first multi-input/output Serial Peripheral Interface coupled to the NOR flash memory array and having a plurality of configurable pins configurable as a single Serial Peripheral Interface or as a quad Serial Peripheral Interface to provide access to the NOR flash memory array;
a second chip comprising:
a NAND flash memory array specialized for data storage; and
a second multi-input/output Serial Peripheral Interface coupled to the NAND flash memory array and having a plurality of configurable pins configurable as a single Serial Peripheral Interface or as a quad Serial Peripheral Interface in the same manner as the configurable pins of the first multi-input/output Serial Peripheral Interface to provide access to the NAND flash memory array; and
a multi-chip package containing the first chip and the second chip and comprising a plurality of pins mounted thereon, at least some of the pins of the multi-chip package being configurable pins, and each of the configurable pins of the multi-chip package being coupled to respective same-type configurable pins of the first and second multi-input/output Serial Peripheral Interfaces.
2. A flash memory as in claim 1 wherein the pins of the multi-chip package consist of eight pins common to pins of both the first multi-input/output Serial Peripheral Interface and the second multi-input/output Serial Peripheral Interface, the eight pins respectively being a power pin, a ground pin, a clock pin, a chip select pin, a configurable hold or input/output pin, a configurable write-protect or input/output pin, a configurable data out or input/output pin, and a configurable data in or input/output pin.
3. A flash memory as in claim 2 wherein:
the first multi-input/output Serial Peripheral Interface is further configurable as a dual Serial Peripheral Interface;
the second multi-input/output Serial Peripheral Interface is further configurable as a dual Serial Peripheral Interface; and
the pins of the multi-chip package are further configurable in a dual serial configuration to provide access to the NOR flash memory array and to the NAND flash memory array.