Three-dimensional memory comprising an integrated intermediate-circuit die
The present invention discloses a discrete three-dimensional memory (3D-M). It comprises at least a 3D-array die and at least an integrated intermediate-circuit die comprising both a read/write-voltage generator (V R /V W -generator) and an address/data translator (A/D-translator). The intermediate-circuit die performs voltage, address and/or data conversion between the 3D-M core region and the host. Discrete 3D-M support multiple 3D-array dies.
1. A discrete three-dimensional memory (3D-M), comprising:
a 3D-array die comprising at least a 3D-M array including a plurality of vertically stacked memory levels;
an intermediate-circuit die comprising at least a first portion of a read/write-voltage generator and at least a second portion of an address/data translator, wherein said read/write-voltage generator provides said 3D-array die with at least a read voltage and/or a write voltage other than the voltage supply, and said address/data translator converts at least an address and/or data between a host and said 3D-array die;
wherein said first portion of said read/write-voltage generator and said second portion of said address/data translator are absent from said 3D-array die; said 3D-array die comprises more back-end layers than said intermediate-circuit die; and, said 3D-array die and said intermediate-circuit die are separate dice.
2. The discrete 3D-M according to claim 1 , wherein said read/write-voltage generator comprises a DC-to-DC converter.
3. The discrete 3D-M according to claim 1 , wherein said address/data translator is an address translator comprising at least one of an address mapping table, a faulty block table and a wear management table.
4. The discrete 3D-M according to claim 1 , wherein said address/data translator is a data translator comprising at least one of an ECC-encoder and an ECC-decoder.
5. The discrete 3D-M according to claim 1 , wherein said 3D-M comprises a three-dimensional read-only memory (3D-ROM) or a three-dimensional random-access memory (3D-RAM).
6. The discrete 3D-M according to claim 5 , wherein said 3D-ROM is a three-dimensional mask-programmed read-only memory (3D-MPROM), or a three-dimensional electrically-programmable read-only memory (3D-EPROM).
7. The discrete 3D-M according to claim 1 , wherein said 3D-M comprises at least one of a memristor, a resistive random-access memory (RRAM or ReRAM), a phase-change memory (PCM), a programmable metallization cell (PMC), and a conductive-bridging random-access memory (CBRAM).
8. The discrete 3D-M according to claim 1 , wherein at least one of said 3D-array die and said intermediate-circuit die further comprises a parallel-serial converting means.
9. The discrete 3D-M according to claim 1 , wherein said 3D-array die and said intermediate-circuit die are located in a memory package, a memory module, a memory card or a solid-state drive.
10. The discrete 3D-M according to claim 1 , further comprising another 3D-array die including at least another 3D-M array, wherein said intermediate-circuit die further comprises at least a third portion of another read/write-voltage generator and at least a fourth portion of another address/data translator for said another 3D-array die.
11. A discrete three-dimensional memory (3D-M), comprising:
a 3D-array die comprising at least a 3D-M array including a plurality of vertically stacked memory levels;
an intermediate-circuit die comprising at least a first portion of a read/write-voltage generator and at least a second portion of an address/data translator, wherein said read/write-voltage generator provides said 3D-array die with at least a read voltage and/or a write voltage other than the voltage supply, and said address/data translator converts at least an address and/or data between a host and said 3D-array die;
wherein said first portion of said read/write-voltage generator and said second portion of said address/data translator are absent from said 3D-array die; said intermediate-circuit die comprises at least one different interconnect material than said 3D-array die; and, said 3D-array die and said intermediate-circuit die are separate dice.
12. The discrete 3D-M according to claim 11 , wherein the interconnect materials of said 3D-array die are stable at a higher processing temperature than the interconnect materials of said intermediate-circuit die.
13. The discrete 3D-M according to claim 11 , wherein at least an interconnect material of said intermediate-circuit die has a higher electrical conductivity than at least another interconnect material of said 3D-array die.
14. The discrete 3D-M according to claim 11 , wherein said 3D-M comprises a three-dimensional read-only memory (3D-ROM) or a three-dimensional random-access memory (3D-RAM).
15. The discrete 3D-M according to claim 11 , wherein said 3D-array die and said intermediate-circuit die are located in a memory package, a memory module, a memory card or a solid-state drive.
16. The discrete 3D-M according to claim 11 , further comprising another 3D-array die including at least another 3D-M array, wherein said intermediate-circuit die further comprises at least a third portion of another read/write-voltage generator and at least a fourth portion of another address/data translator for said another 3D-array die.
17. A discrete three-dimensional memory (3D-M), comprising:
a 3D-array die comprising at least a 3D-M array including a plurality of vertically stacked memory levels;
an intermediate-circuit die comprising at least a first portion of a read/write-voltage generator and at least a second portion of an address/data translator, wherein said read/write-voltage generator provides said 3D-array die with at least a read voltage and/or a write voltage other than the voltage supply, and said address/data translator converts at least an address and/or data between a host and said 3D-array die;
wherein said first portion of said read/write-voltage generator and said second portion of said address/data translator are absent from said 3D-array die; said intermediate-circuit die comprises more substrate interconnect layers than said 3D-array die; and, said 3D-array die and said intermediate-circuit die are separate dice.
18. The discrete 3D-M according to claim 17 , wherein said 3D-M comprises a three-dimensional read-only memory (3D-ROM) or a three-dimensional random-access memory (3D-RAM).
19. The discrete 3D-M according to claim 17 , wherein said 3D-array die and said intermediate-circuit die are located in a memory package, a memory module, a memory card or a solid-state drive.
20. The discrete 3D-M according to claim 17 , further comprising another 3D-array die including at least another 3D-M array, wherein said intermediate-circuit die further comprises at least a third portion of another read/write-voltage generator and at least a fourth portion of another address/data translator for said another 3D-array die.