Intelligent metamodel integrated Verilog-AMS for fast and accurate analog block design exploration

1. A method for modeling a circuit comprising:

storing a plurality of design variable ranges for a circuit component in a non-transient electronic data memory;

performing transistor-level simulations at a plurality of sample points for the circuit component using a processor to generate a plurality of design variable samples for the circuit component and generating a plurality of circuit response samples;

selecting and storing a neural network architecture in the non-transient electronic data memory that models the plurality of design variable samples for the circuit component; and

generating a performance metric metamodel and a circuit parameter metamodel based on the neural network architecture using a processor operating Verilog-AMS;

storing the performance metric metamodel and the circuit parameter metamodel;

training the neural network architecture with a processor using the design variable samples and the circuit response samples; and

generating one or more analog block metamodels using the trained neural network architecture.

2. The method of claim 1 further comprising adjusting sample points for the transistor-level simulations using the processor if a predetermined accuracy is not met.

3. The method of claim 1 further comprising adjusting the architecture of the neural network using the processor if a predetermined accuracy is not met.

4. A method for modeling a circuit comprising:

(a) determining a range for each of a plurality of design variables using a processor;

(b) determining a sample number for a circuit component using the processor;

(c) performing an analog block design space sample with transistor level simulations of the circuit component to generate design variable samples and circuit response samples for the circuit component;

(d) performing neural network training on the processor to generate a neural network architecture;

(e) storing an analog block metamodel that comprises the neural network architecture in a non-transient data memory;

(f) determining whether a predetermined accuracy metric has been met or exceeded an estimate constraint based on the neural network architecture with the processor;

(g) repeating steps (a) through (f) if the accuracy metric has not been met or exceeded the estimate constraint; and

(h) generating a performance metric metamodel and a circuit parameter metamodel based on the neural network architecture with the processor if the accuracy metric has been met or exceeded the estimate constraint.

5. The method of claim 4 wherein performing the neural network training on the processor to generate the neural network architecture comprises performing sample data verification.

6. The method of claim 4 wherein performing the neural network training on the processor to generate the neural network architecture comprises performing performance metamodel verification.

7. The method of claim 4 wherein performing the neural network training on the processor to generate the neural network architecture comprises performing parameter metamodel verification.

8. The method of claim 4 wherein performing the neural network training on the processor to generate the neural network architecture comprises performing statistical sample training.

9. The method of claim 4 wherein performing the neural network training on the processor to generate the neural network architecture comprises performing performance training.

10. The method of claim 4 wherein performing the neural network training on the processor to generate the neural network architecture comprises performing circuit parameter training.

11. The method of claim 4 further comprising integrating the performance metric metamodel and the circuit parameter metamodel using Verilog-AMS operating on the processor.

12. The method of claim 4 further comprising integrating the performance metric metamodel and the circuit parameter metamodel with a macromodel using Verilog-AMS operating on the processor.

13. The method of claim 4 wherein repeating steps (a) through (f) if the accuracy metric has not been met or exceeded comprises modifying the sample number for the circuit component.

14. The method of claim 4 wherein repeating steps (a) through (f) if the accuracy metric has not been met or exceeded comprises modifying the neural network architecture.

15. A method for modeling a circuit comprising:

(a) determining a range for each of a plurality of design variables using a processor;

(b) determining a sample number for a circuit component using the processor;

(c) performing an analog block design space sample with transistor level simulations of the circuit component to generate design variable samples and circuit response samples for the circuit component;

(d) performing neural network training on the processor to generate a neural network architecture with sample data verification, performance metamodel verification, parameter metamodel verification, statistical sample training, performance training and circuit parameter training;

(e) storing an analog block metamodel that comprises the neural network architecture in a non-transient data memory;

(f) determining whether a predetermined accuracy metric has been met or exceeded an estimate constraint based on the neural network architecture with the processor;

(g) repeating steps (a) through (f) if the accuracy metric has not been met or exceeded the estimate constraint by modifying the sample number for the circuit component and modifying the neural network architecture;

(h) generating a performance metric metamodel and a circuit parameter metamodel based on the neural network architecture with the processor if the accuracy metric has been met or exceeded the estimate constraint;

(i) integrating the performance metric metamodel and the circuit parameter metamodel with a macromodel using Verilog-AMS operating on the processor.