Through silicon via in n+ epitaxy wafers with reduced parasitic capacitance

1. A semiconductor device comprising:

an epitaxy layer formed on a semiconductor substrate;

a device layer formed on the epitaxy layer;

an opening formed within the semiconductor substrate and including a dielectric layer forming a liner and a conductive core within the opening forming a signal through-silicon via, wherein the signal through-silicon via extends through the device layer and the epitaxy layer; and

an isolating through-silicon via formed within the substrate and surrounding the signal through-silicon via, wherein the isolating through-silicon via extends through the device layer and the epitaxy layer, such that the isolating through-silicon via forms a ring around the signal through-silicon via, wherein a region of the epitaxy layer formed inside the ring between the isolating through-silicon via and the signal through-silicon via is electrically isolated from another region of the epitaxy layer that is formed outside the ring when a voltage is applied to the signal through-silicon via.

2. The semiconductor device of claim 1 , wherein the signal through-silicon via is of a larger depth in the substrate and larger width than a depth and a width of the isolating through-silicon via.

3. The semiconductor device of claim 1 , wherein the region of the epitaxy layer is formed of a predetermined thickness ranging from approximately 1 micrometer to approximately 10 micrometers.

4. The semiconductor device of claim 1 , wherein the epitaxy layer is an n+ epitaxy layer.

5. The semiconductor device of claim 4 , wherein the epitaxy layer has a doping level above approximately of about 1×10 19 atoms/cm 3 or greater.