Bandgap reference circuit and regulator circuit with common amplifier
A bandgap voltage reference and voltage regulator system includes a bandgap voltage reference circuit and a voltage regulator circuit that share a single, common amplifier. The amplifier acts as a gain stage for the reference circuit and as an error amplifier for a driver stage of the regulator circuit. The regulator circuit has an input reference generated by the reference circuit, and the reference circuit acts as a load to the driver stage, obviating the need for a bias resistance network. By sharing the amplifier and obviating the need for a resistance network, the area and overall quiescent current of the system are reduced. The system can be implemented in CMOS/BiCMOS technology and is suited for low power applications.
1. A bandgap voltage reference and voltage regulator system, comprising:
a bandgap voltage reference circuit;
a voltage regulator circuit having a driver stage;
an operational amplifier having an inverted input and a non-inverted input, wherein the operation amplifier is connected between the bandgap voltage reference circuit and the voltage regulator circuit, wherein the operational amplifier is shared by the bandgap voltage reference circuit and the voltage regulator circuit, and wherein the operational amplifier operates as a gain stage for the bandgap voltage reference circuit, and as an error amplifier for the driver stage of the voltage regulator circuit; and
a start-up circuit directly connected to the inverted and non-inverted inputs of the operational amplifier, and to the output of the operational amplifier for detecting a regulator output voltage level and bringing up the system to a predetermined operating point,
wherein the operational amplifier comprises:
a first stage including the inverted and non-inverted inputs of the operational amplifier;
a second stage connected to the first stage, for providing a drive voltage (Vdriver) at the output of the operational amplifier; and
a current reference stage connected to the second stage and comprising elements from the first stage of the operational amplifier,
wherein the first stage of the operational amplifier comprises:
an input differential section including first and second input differential section transistors;
a load section including first and second load section transistors; and
a tail current source section including a tail current source section transistor, wherein:
the first input differential section transistor has a source connected to a source of the second input differential section transistor and to a drain of the tail current source section transistor, a gate connected to the inverted input of the operational amplifier, and a drain connected to a drain of the first load section transistor,
the second input differential section transistor has a gate connected to the non-inverted input of the operational amplifier, and a drain connected to a drain of the second load section transistor,
the first load section transistor has a gate connected to its drain and to a gate of the second load section transistor, and a source connected to a source of the second load section transistor and to a common ground (Vss),
the tail current source section transistor has a gate connected to the second stage and a source connected to a supply voltage (Vdd), and
wherein an output of the first stage is generated at a node between the drains of the second input differential section transistor and the second load section transistor.
2. The system of claim 1 , wherein the bandgap voltage reference circuit comprises:
a first core transistor;
a second core transistor having a base and a collector connected together to a common ground (Vss) and to a base and a collector of the first core transistor;
a first core resistor having a first end connected to an emitter of the second core transistor;
a second core resistor having a first end connected to an emitter of the first core transistor, and a second end connected to an operating voltage (Vbgr); and
a third core resistor having a first end connected to a second end of the first core resistor and a second end connected to the operating voltage (Vbgr),
wherein the inverted input of the operational amplifier is connected to a node between the first and third core resistors and the non-inverted input of the operational amplifier is connected to a node between the second core resistor and the emitter of the first core transistor.
3. The system of claim 2 , wherein the first and second core transistors are parasitic bi-polar transistors.
4. The system of claim 3 , wherein an emitter area of the second core transistor is larger than an emitter area of the first core transistor.
5. The system of claim 2 , wherein the driver stage of the voltage regulator circuit comprises:
a driver stage transistor having a drain connected to a supply voltage (Vdd), a gate connected to an output of the operational amplifier, and a source connected to the output of the operational amplifier and to a node between the operating voltage (Vbgr) and the second ends of the second and third core resistors,
wherein the drive voltage (Vdriver) is provided at the output of the operational amplifier, and the regulator output voltage (Vout) is provided at the source of the driver stage transistor.
6. The system of claim 1 , wherein the second stage of the operational amplifier comprises:
a first second-stage transistor having a source connected to the supply voltage (Vdd), and a gate connected to the gate of the tail current source section transistor; and
a second second-stage transistor having a source connected to the common ground (Vss), a drain connected to a drain of the first second-stage transistor, wherein the operational amplifier output voltage (Vdriver) is generated at a node between the drains of the first and second second-stage transistors, and a gate connected to a node between the drains of the second input differential section transistor and the second load section transistor of the first stage.
7. The system of claim 6 , wherein the current reference stage of the operational amplifier comprises:
the first input differential section transistor, the first load section transistor, and the tail current source section transistor of the first stage;
a first current reference stage transistor having a source connected by way of a resistor to the common ground (Vss), and a gate connected to the gates of the first and second load section transistors and the drain of the first load section transistor; and
a second current reference stage transistor having a source connected to the supply voltage (Vdd), a drain connected to the drain of the first current reference stage transistor, and a gate connected to its drain and to the gates of the tail current source section transistor and the first second stage transistor.
8. The system of claim 1 , wherein the start-up circuit comprises:
a voltage divider connected between the supply voltage (Vdd) and the common ground (Vss);
a comparator having a non-inverted input connected to the voltage divider, an inverted input connected to the source of the driver stage transistor and receiving the output voltage (Vout), and an output;
a first inverter having an input connected to the output of the comparator;
a second inverter having an input connected to the output of the first inverter;
a first start-up circuit transistor having a drain connected to the supply voltage (Vdd), a source connected to the output of the operational amplifier and receiving the drive voltage (Vdriver), and a gate connected to an output of the second inverter, and wherein a bulk connected to the common ground (Vss);
a second start-up circuit transistor having a drain connected to the inverted input of the operational amplifier, and a source connected to the common ground (Vss);
a third start-up circuit transistor having a drain connected to the non-inverted input of the operational amplifier, a source connected to the common ground (Vss), and a gate connected to the gate of the second start-up circuit transistor, and wherein the gates of the second and third start-up circuit transistors are connected to the output of the second inverter;
a fourth start-up circuit transistor having source connected to the inverted input of the comparator and receiving the output voltage (Vout), a drain connected to the operating voltage (Vbgr), and a gate connected to the gates of the second and third start-up circuit transistors and the output of the second inverter; and
a capacitor connected between the output of the comparator and the supply voltage (Vdd).
9. The system of claim 8 , wherein the voltage divider comprises:
a first voltage divider transistor;
a second voltage divider transistor; and
a third voltage divider transistor,
wherein the first voltage divider transistor has a drain and a gate connected together and to the supply voltage (Vdd);
the second voltage divider transistor has a drain and a gate connected to a source of the first voltage divider transistor; and
the third voltage divider transistor has a drain and a gate connected together and to the source of the second voltage divider transistor, and a source connected to the common ground (Vss).
10. The system of claim 9 , wherein the non-inverted input of the comparator is connected to the drain of the third voltage divider transistor and a fraction of the supply voltage (Vdd) is provided to the non-inverted input of the comparator.
11. The system of claim 10 , wherein the fraction of the supply voltage (Vdd) derived at the non-inverted input of the comparator is Vdd/3.