Definition of wakeup bus messages for partial networking
A method of encoding a digital bus message information, in particular a wake-up bus message information or configuring data, on a bus system, the method comprising: encoding a predetermined part of digital bus message information bits by means of sub-patterns in a stream of line symbols on at least one bus line, wherein sub-patterns consist of successive dominant and recessive phases, comprised of recessive and dominant line symbols, wherein a recessive phase is comprised of at least two recessive line symbols in order to establish a ratio of successive dominant and recessive phases that corresponds to a value of the predetermined part. A respective digital bus message, particularly for use on a bus system, is to be encoded in accordance with the method. Further, a bus node for a system bus having a plurality of stations that are coupled together by means of an arrangement of bus lines, comprises decoding circuitry configured for an analysis of sub-patterns in a stream of data on at least one bus line, and analysing circuitry configured to detect encoded digital bus message information, in particular a wake-up bus message information or configuring data, transmitted in a stream of line symbols on the bus system, wherein the digital bus message information is encoded in accordance with the method.
1. A method of encoding a digital bus message information, the method comprising:
encoding a predetermined part of digital bus message information bits by sub-patterns in a stream of line symbols on at least one bus line, wherein sub-patterns consist of successive dominant and recessive phases, comprised of recessive and dominant line symbols, respectively,
wherein a recessive phase is comprised of at least two recessive line symbols in order to establish a ratio of successive dominant and recessive phases of the sub-pattern that corresponds to a value of the predetermined part, wherein consecutive sub-patterns are equal in length.
2. A method as claimed in claim 1 , the method further comprising:
representing a dominant or recessive, respectively, bit of the digital bus message information by the length of the dominant phase being longer or shorter, respectively, than that of the succeeding recessive phase.
3. A method as claimed in claim 1 ,
the method further comprising:
encoding a series of digital relative information by consecutive sub-patterns by a number of line symbols used in each sub-pattern with respect to a preceding sub-pattern, wherein preferably consecutive sub-patterns have equal lengths.
4. A method as claimed in claim 1 ,
wherein the digital bus message information comprises at least an identifier field and a data field, and
the method further comprises:
determining the predetermined part of the digital bus message information bits to cover the data field and at least partly the identifier field and/or a part between the identifier field and the data field.
5. A method as claimed in claim 1 ,
wherein the digital bus message information comprises a data length code field, and
the method further comprises:
using of data length codes greater than decimal 8.
6. A method as claimed in claim 1 ,
wherein the predetermined part of the digital bus message information bits covers an identifier field of the digital bus message information only partly, wherein the first 4 bits of the identifier field are not used and following two bits are recessive bits.
7. A method as claimed in claim 6 ,
wherein an identifier field of the digital bus message information comprises 29 bits.
8. A method as claimed in claim 1 ,
wherein the digital bus message is a message in accordance with one of a controller area network protocol, a local interconnect network protocol, and a FlexRay protocol.
9. A digital bus message,
wherein the digital bus message information is encoded in accordance with a method as claimed in claim 1 .
10. A pattern detector for a bus node for a system bus having a plurality of stations that are coupled together by an arrangement of bus lines, the pattern detector comprising:
decoding circuitry configured for an analysis of sub-patterns in a stream of data on at least one bus line, and
analysing circuitry configured to detect encoded digital bus message information, transmitted in a stream of line symbols on the bus system, wherein the digital bus message information is encoded in accordance with a method as defined in claim 1 .
11. A bus node chip comprising:
at least one pattern detector according to claim 10 ,
a microcontroller:
a transmit pin configured to receive a signal from the microcontroller;
a receive pin configured to transmit a signal to the microcontroller; and
a bus pin configured to transmit and receive signalling on at least one of the bus lines.
12. A bus system having a plurality of stations that are coupled together by an arrangement of bus lines and at least one station having a bus node chip according to claim 11 .
13. A method of encoding a digital bus message information, the method comprising:
encoding a predetermined part of digital bus message information bits by sub-patterns in a stream of line symbols on at least one bus line, wherein sub-patterns consist of successive dominant and recessive phases, comprised of recessive and dominant line symbols, respectively, wherein a recessive phase is comprised of at least two recessive line symbols in order to establish a ratio of successive dominant and recessive phases of the sub-pattern that corresponds to a value of the predetermined part; and
encoding a series of digital relative information by consecutive sub-patterns by a number of line symbols used in each sub-pattern with respect to a preceding sub-pattern, wherein preferably consecutive sub-patterns have equal lengths.
14. A method of encoding a digital bus message information, the method comprising:
encoding a predetermined part of digital bus message information bits by sub-patterns in a stream of line symbols on at least one bus line, wherein sub-patterns consist of successive dominant and recessive phases, comprised of recessive and dominant line symbols, respectively, wherein a recessive phase is comprised of at least two recessive line symbols in order to establish a ratio of successive dominant and recessive phases of the sub-pattern that corresponds to a value of the predetermined part, wherein the predetermined part of the digital bus message information bits covers an identifier field of the digital bus message information only partly.
15. The method of claim 14 , wherein the first 4 bits of the identifier field are not used and following two bits are recessive bits.