Nanometer-scale level structures and fabrication method for digital etching of nanometer-scale level structures
A ramped etalon cavity structure and a method of fabricating same. A bi-layer stack is deposited on a substrate. The bi-layer stack includes a plurality of bi-layers. Each bi-layer of the plurality of bi-layers includes an etch stop layer and a bulk layer. A three dimensional photoresist structure is formed by using gray-tone lithography. The three dimensional photoresist is plasma etched into the bi-layer stack, thereby generating an etched bi-layer stack. The etched bi-layer stack is chemically etched with a first chemical etchant to generate a multiple-step structure on the substrate, wherein the first chemical etchant stops at the etch stop layer.
1. A method of fabricating a multiple-step structure on a substrate, the method comprising:
depositing a bi-layer stack on a substrate, the bi-layer stack comprising a plurality of bi-layers, each bi-layer of the plurality of bi-layers comprising an etch stop layer and a bulk layer;
forming a three dimensional photoresist structure by using gray-tone lithography;
plasma etching the three dimensional photoresist into the bi-layer stack, thereby generating an etched bi-layer stack; and
chemically etching the etched hi-layer stack with a first chemical etchant to generate a multiple-step structure on the substrate, wherein the first chemical etchant stops at the etch stop layer.
2. The method according to claim 1 , wherein the etch stop layer comprises alumina, and the bulk layer comprises silicon oxide.
3. The method according to claim 1 , wherein the first chemical etchant comprises vaporous hydrofluoric acid.
4. The method according to claim 1 , wherein said plasma etching the three dimensional photoresist into the bi-layer stack comprises fluorine-based plasma chemistry.
5. The method according to claim 1 , wherein the multiple-step structure comprises a number of individual steps, the number of individual steps being larger than twenty.
6. The method according to claim 1 , wherein the substrate is a semiconductor with integrated circuits.
7. The method according to claim 1 , wherein the substrate is a focal plane array comprising a plurality of sensor nodes.
8. The method according to claim 6 , wherein said semiconductor is an imager.
9. The method according to claim 1 , wherein said depositing a bi-layer stack comprises depositing the plurality of bi-layers by one of atomic layer deposition, sputtering, and evaporation.
10. The method according to claim 1 , further comprising:
chemically etching the etched bi-layer stack with a second chemical etchant to generate a multiple-step structure on the substrate, wherein the second chemical etchant stops at the bulk layer.
11. A device comprising:
a substrate; and
a plurality of etalon optical cavities on said substrate, each etalon optical cavity of said plurality of etalon optical cavities comprising two mirrors sandwiching a bi-layer stack, said bi-layer stack comprising a plurality of bi-layers, each bi-layer of said plurality of bi-layers comprising an etch stop layer and a bulk layer, wherein said etch stop layer and said bulk layer are index-matched sufficiently close so as to permit multiple internal reflections within said each etalon optical cavity.
12. The device according to claim 11 , wherein said etalon cavities comprise a top surface roughness less than 3 nm root mean squared.
13. The device according to claim 11 , wherein said etch stop layer comprises alumina, and said bulk layer comprises silicon oxide.
14. The device according to claim 11 , wherein said substrate comprises one of a focal plane array, a CMOS imager, a CCD array, and a semiconductor device.
15. The device according to claim 14 , wherein said focal plane array comprises a plurality of sensor nodes.
16. The device according to claim 15 , wherein said plurality of sensor nodes comprises a plurality of photodiodes.
17. The device according to claim 1 , wherein said two mirrors comprise a top mirror and a bottom mirror, one of said top mirror and said bottom mirror comprising a metal layer.
18. The device according to claim 1 wherein said two mirrors comprise a top mirror and a bottom mirror, one of said top mirror and said bottom mirror comprising an adhesive and a metal layer.
19. The device according to claim 1 wherein said two mirrors comprise a top mirror and a bottom mirror, one of said top mirror and said bottom mirror comprising a dielectric mirror.
20. The device according to claim 11 , wherein said two mirrors comprise a top mirror and a bottom mirror, one of said top mirror and said bottom mirror comprising a material boundary where reflection is due to differences in refractive index.