Delay locked loop and method of generating clock

1. A delay locked loop (DLL) comprising:

a ring oscillator (RO) including a delay line to delay a reference clock signal and generate a delayed clock signal, wherein the RO circulates, through the delay line, a feedback clock signal corresponding to the delayed clock signal to synchronize N cycles of the feedback clock signal with a cycle of the reference clock signal (where N is an integer number equal to or larger than 2); and

a first frequency divider dividing the frequency of the delayed clock signal by 1/N (where N is an integer number equal to or larger than 2) to generate an output clock signal,

wherein the RO selects at least one of the reference clock signal and the feedback clock signal as an input clock signal based on the feedback clock signal to input the selected signal to the delay line;

wherein after the feedback clock signal circulates, N times, through the RO, the RO selects the reference clock signal as the input clock signal and inputs the selected reference clock signal to the delay line; and

wherein in response to a rising edge of the reference clock signal, the RO selects the feedback clock signal as the input clock signal and inputs the selected feedback clock signal to the delay line.

2. The delay locked loop (DLL) of claim 1 , wherein the RO comprises:

a signal selection unit selecting the at least one of the reference clock signal and the feedback clock signal as the input clock signal based on the feedback clock signal to input the selected signal to the delay line; and

a delay control unit comparing N cycles of the feedback clock signal with a cycle of the reference clock signal to adjust a delay time of the delay line, wherein the delay line delays the input clock signal to generate the delayed clock signal.

3. The delay locked loop (DLL) of claim 2 , wherein the RO further comprises a dummy delay unit that delays the delayed clock signal by the delay time of the first frequency divider to generate the feedback clock signal.

4. The delay locked loop (DLL) of claim 2 , wherein after the feedback clock signal circulates, N times, through the RO, the signal selection unit selects the reference clock signal as the input clock signal and inputs the selected signal to the delay line, and in response to the rising edge of the reference clock signal, the signal selection unit selects the feedback clock signal as the input clock signal and inputs the selected signal to the delay line.

5. A delay locked loop (DLL) comprising:

a ring oscillator (RO) including a delay line to delay a reference clock signal and generate a delayed clock signal, wherein the RO circulates, through the delay line, a feedback clock signal corresponding to the delayed clock signal to synchronize N cycles of the feedback clock signal with a cycle of the reference clock signal (where N is an integer number equal to or larger than 2); and

a first frequency divider dividing the frequency of the delayed clock signal by 1/N (where N is an integer number equal to or larger than 2) to generate an output clock signal,

wherein the RO comprises:

a signal selection unit selecting at least one of the reference clock signal and the feedback clock signal as an input clock signal based on the feedback clock signal to input the selected signal to the delay line; and

a delay control unit comparing N cycles of the feedback clock signal with a cycle of the reference clock signal to adjust a delay time of the delay line, wherein the delay line delays the input clock signal to generate the delayed clock signal, wherein the delay control unit comprises:

a phase detector comparing N cycles of the feedback clock signal with a cycle of the reference clock signal and generates any one of up, down and lock control signals; and

a counter counting the control signal to generate a control code and inputting the control code to the delay line to adjust the delay time.

6. A delay locked loop (DLL) comprising:

a ring oscillator (RO) including a delay line to delay a reference clock signal and generate a delayed clock signal, wherein the RO circulates, through the delay line, a feedback clock signal corresponding to the delayed clock signal to synchronize N cycles of the feedback clock signal with a cycle of the reference clock signal (where N is an integer number equal to or larger than 2); and

a first frequency divider dividing the frequency of the delayed clock signal by 1/N (where N is an integer number equal to or larger than 2) to generate an output clock signal,

wherein the RO comprises:

a signal selection unit selecting at least one of the reference clock signal and the feedback clock signal as an input clock signal based on the feedback clock signal to input the selected signal to the delay line; and

a delay control unit comparing N cycles of the feedback clock signal with a cycle of the reference clock signal to adjust a delay time of the delay line, wherein the delay line delays the input clock signal to generate the delayed clock signal, wherein the signal selection unit comprises:

a selection signal generation unit generating a selection signal that has a rising edge or falling edge corresponding to the N circulations of the feedback clock signal and has a falling edge or rising edge corresponding to a rising edge of the reference clock signal; and

a multiplexer selecting the reference clock signal as the input clock signal after the feedback clock signal circulates N times according to the selection signal, and selecting the feedback clock signal as the input clock signal in response to a rising edge of the reference clock signal.

7. The delay locked loop (DLL) of claim 6 , wherein the selection signal generation unit comprises:

a second frequency divider dividing the frequency of the feedback clock signal by 1/N (N is an integer number equal to or larger than 2) to generate a frequency division signal; and

a selection logic generating the selection signal based on the frequency division signal and the reference clock signal.

8. The delay locked loop (DLL) of claim 7 , wherein the second frequency divider generates the rising edge or falling edge corresponding to a falling edge of a Nth pulse of N cycles of the feedback clock signal, generates the falling edge or rising edge corresponding to the rising edge of the reference clock signal, to generate the selection signal.

9. The delay locked loop (DLL) of claim 6 , wherein the selection signal generation unit comprises:

a counter a number of cycles that the feedback clock signal circulates through the RO; and

a comparator comparing the number of cycles of the feedback clock signal with N (where N is an integer number equal to or larger than 2) to generate the selection signal.

10. The delay locked loop (DLL) of claim 9 , wherein after the feedback clock signal circulates N times, the comparator resets the counter to a default value.

11. A delay locked loop (DLL) of claim 1 , comprising:

a ring oscillator (RO) including a delay line to delay a reference clock signal and generate a delayed clock signal, wherein the RO circulates, through the delay line, a feedback clock signal corresponding to the delayed clock signal to synchronize N cycles of the feedback clock signal with a cycle of the reference clock signal (where N is an integer number equal to or larger than 2); and

a first frequency divider dividing the frequency of the delayed clock signal by 1/N (where N is an integer number equal to or larger than 2) to generate an output clock signal,

wherein the first frequency divider generates a rising edge or falling edge corresponding to a first one of 2 N edges of N cycles of the delayed clock signal, generates a falling edge or rising edge corresponding to a N+1th one of the 2 N edges, to generate the output clock signal.

12. The delay locked loop (DLL) of claim 1 , wherein the first frequency divider generates the output clock signal 180°/N phase-shifted from the reference clock signal (N is an integer number equal to or larger than 2).

13. The delay locked loop (DLL) of claim 1 , wherein the first frequency divider generates the output clock signal having a 50% duty cycle.

14. A method of generating a clock, comprising:

inputting a reference clock signal to a delay line to delay the signal to generate a delayed clock signal, and circulating a feedback clock signal corresponding to the delayed clock signal through the delay line to synchronize N cycles of the feedback clock signal (where N is an integer number equal to or larger than 2) with a cycle of the reference clock signal; and

dividing a frequency of the delayed clock signal by 1/N (where N is an integer number equal to or larger than 2) to generate an output clock signal,

wherein the synchronizing of the N cycles of the feedback clock signal comprises:

selecting at least one of the reference clock signal and the feedback clock signal as an input clock signal based on the feedback clock signal,

wherein the selecting of the at least one of the reference clock signal and the feedback clock signal as the input clock signal comprises:

selecting the reference clock signal as the input clock signal and inputting the selected signal to the delay line, after the feedback clock signal circulates N times; and

in response to a rising edge of the reference clock signal, selecting the feedback clock signal as the input clock signal and inputting the selected signal to the delay line.

15. The method of claim 14 , wherein the synchronizing of the N cycles of the feedback clock signal further comprises:

delaying the input clock signal at the delay line to generate the delayed clock signal; and

comparing a cycle of the reference clock signal with N cycles of the feedback clock signal to adjust a delay time of the delay line according to a comparison result.

16. The method of claim 15 , wherein the synchronizing of the N cycles of the feedback clock signal further comprises delaying the delayed clock signal by a delay time of the output clock signal relative to the delayed clock signal to generate the feedback clock signal, after generating the delayed clock signal.

17. A method of generating a clock comprising:

inputting a reference clock signal to a delay line to delay the signal to generate a delayed clock signal, and circulating a feedback clock signal corresponding to the delayed clock signal through the delay line to synchronize N cycles of the feedback clock signal (where N is an integer number equal to or larger than 2) with a cycle of the reference clock signal; and

dividing a frequency of the delayed clock signal by 1/N (where N is an integer number equal to or larger than 2) to generate an output clock signal,

wherein the synchronizing of the N cycles of the feedback clock signal comprises:

selecting at least one of the reference clock signal and the feedback clock signal as an input clock signal based on the feedback clock signal;

delaying the input clock signal at the delay line to generate a delayed clock signal; and

comparing a cycle of the reference clock signal with N cycles of the feedback clock signal to adjust a delay time of the delay line according to a comparison result,

wherein the selecting of the at least one of the reference clock signal and the feedback clock signal as the input clock signal comprises:

generating a selection signal in response to N circulations of the feedback clock signal (where N is an integer number equal to or larger than 2) and a rising edge of the reference clock signal; and

selecting the at least one of the feedback clock signal and the reference clock signal as the input clock signal according to the selection signal and inputting the selected signal to the delay line.

18. A method of generating a clock comprising:

inputting a reference clock signal to a delay line to delay the signal to generate a delayed clock signal, and circulating a feedback clock signal corresponding to the delayed clock signal through the delay line to synchronize N cycles of the feedback clock signal (where N is an integer number equal to or larger than 2) with a cycle of the reference clock signal; and

dividing a frequency of the delayed clock signal by 1/N (where N is an integer number equal to or larger than 2) to generate an output clock signal,

wherein the generating of the output clock signal comprises generating a rising edge or falling edge in response to a first one of 2 N edges of N cycles of the delayed clock signal, generating a falling edge or rising edge in response to a N+1th one of the 2 N edges, to generate the output clock signal.

19. A method of generating a clock comprising:

inputting a reference clock signal to a delay line to delay the signal to generate a delayed clock signal, and circulating a feedback clock signal corresponding to the delayed clock signal through the delay line to synchronize N cycles of the feedback clock signal (where N is an integer number equal to or larger than 2) with a cycle of the reference clock signal; and

dividing a frequency of the delayed clock signal by 1/N (where N is an integer number equal to or larger than 2) to generate an output clock signal,

wherein the synchronizing of the N cycles of the feedback clock signal comprises:

selecting at least one of the reference clock signal and the feedback clock signal as an input clock signal based on the feedback clock signal,

wherein the selecting of the at least one of the reference clock signal and the feedback clock signal as the input clock signal comprises:

selecting the reference clock signal as the input clock signal and inputting the selected signal to the delay line, after the feedback clock signal circulates N times; and

in response to a rising edge of the reference clock signal, selecting the feedback clock signal as the input clock signal and inputting the selected signal to the delay line,

wherein the generating of the output clock signal comprises generating the output clock signal 180°/N phase-shifted from the reference clock signal (where N is an integer number equal to or larger than 2).