Stretchable electronic device and method of manufacturing same
Provided are a stretchable electronic device and a method of manufacturing the same. The manufacturing method includes forming coil interconnection on a first substrate, forming a first stretchable insulating layer that covers the coil interconnection, forming a second substrate on the first stretchable insulating layer, separating the first substrate from the coiling interconnection and the first stretchable insulating layer, and forming a transistor on the coil interconnection.
1. A method of manufacturing a stretchable electronic device, the method comprising:
forming coil interconnections on a first substrate;
forming a first stretchable insulating layer that covers the coil interconnection;
forming a second substrate on the first stretchable insulating layer;
separating the first substrate from the coiling interconnection and the first stretchable insulating layer; and
forming a transistor on the coil interconnection.
2. The method of claim 1 , wherein the forming of the coil interconnection comprises:
forming a sacrificial layer on the first substrate;
forming first interconnections on the sacrificial layer;
forming pillar interconnections on the first interconnections; and
forming second interconnections on the pillar interconnections.
3. The method of claim 2 , wherein the sacrificial layer comprises a photoresist, polysilicon, silicon oxide, or silicon nitride film.
4. The method of claim 2 , wherein the separating of the first substrate comprises removing the sacrificial layer.
5. The method of claim 4 , wherein the forming of the first interconnections comprises:
forming a first seed layer on the sacrificial layer;
forming a first photoresist pattern on a part of the first seed layer; and
forming a first cap interconnection layer on the first seed layer exposed by the first photoresist pattern.
6. The method of claim 5 , further comprising, after the forming of the first interconnections, removing the first photoresist pattern.
7. The method of claim 5 , wherein the first cap interconnection layer is formed by an electroplating method.
8. The method of claim 5 , wherein the forming of the pillar interconnections comprises:
forming a second photoresist pattern layer on the first cap interconnection layer and the first seed layer; and
forming pillar interconnection on the first cap interconnection layer.
9. The method of claim 8 , wherein the forming of the second interconnections comprises:
forming a second seed layer on the pillar interconnection and the second photoresist pattern;
forming a third photoresist pattern on a part of the second seed layer; and
forming a second cap interconnection layer on the second seed layer exposed from the third photoresist pattern.
10. The method of claim 9 , wherein the forming of the coil interconnection further comprises removing the third photoresist pattern and the second seed layer exposed from the second cap interconnection layer.
11. The method of claim 10 , wherein the second seed layer is etched.
12. The method of claim 9 , further comprising removing the second photoresist pattern and the first seed layer exposed from the first cap interconnection layer.
13. The method of claim 12 , wherein the first seed layer is etched.
14. The method of claim 1 , further comprising:
after the forming of the transistor, forming a second stretchable insulating layer; and
removing the second substrate.