Method and apparatus for a trust processor

1. An apparatus comprising:

a system-on-a-chip including:

an application processor to execute a driver, the driver to generate a primitive instruction in response to a request for a security service;

direct memory access logic; and

a cryptographic processor comprising:

at least one cryptographic unit;

an interface to receive the primitive instruction from the application processor through the direct memory access logic;

an instruction buffer to store the primitive instruction received by the interface;

a nonvolatile memory to store a plurality of microcode instructions, wherein one or more of the plurality of microcode operations is to cause the cryptographic processor to perform one or more of a plurality of operations including one or more sensitive operations; and

a controller to retrieve the primitive instruction from the instruction buffer and one or more microcode instructions for the primitive instruction from the nonvolatile memory, determine whether at least one of the one or more microcode instructions is to cause the cryptographic processor to perform a sensitive operation, determine whether the cryptographic processor is within a trusted state based on whether the cryptographic processor is properly initialized, control execution of the at least one microcode instruction by the at least one cryptographic unit if the cryptographic processor is in the trusted state or if the at least one microcode instruction is to cause the cryptographic processor to perform a sensitive operation, and preclude execution of the at least one microcode instruction when the cryptographic processor is in an untrusted state and the at least one microcode instruction is to cause the cryptographic processor to perform a sensitive operation.

2. The apparatus of claim 1 , wherein the system-on-a-chip also includes:

a volatile memory to store a cache of at least one cryptographic key and a counter, and

at least one platform configuration register.

3. The apparatus of claim 2 , wherein a sensitive operation is an operation that uses a root encryption key for the apparatus, an operation that uses one of the at least one cryptographic key, or an operation that is to access the counter or the at least one platform configuration register.

4. The apparatus of claim 1 , wherein an illegal operation includes an out-of-order execution by one of the at least one cryptographic units.

5. The apparatus of claim 1 , wherein determining that the at least one microcode instruction is to cause the cryptographic processor to perform the sensitive operation comprises determining that the at least one microcode instruction does not use a root encryption key of the cryptographic processor.

6. The apparatus of claim 1 , wherein determining that the at least one microcode instruction is to cause the cryptographic processor to perform the sensitive operation comprises determining that the at least one microcode instruction does not use an encryption key protected within the cryptographic processor.

7. The apparatus of claim 1 , wherein determining that the at least one microcode instruction is to cause the cryptographic processor to perform the sensitive operation comprises determining that the at least one microcode instruction does not access a monotonic counter or data in a platform configuration register.

8. The apparatus of claim 1 , wherein determining whether the cryptographic processor is within a trusted state based on whether the cryptographic processor is properly initialized further comprises verifying whether at least one functional unit in the cryptographic processor is generating proper results.

9. The apparatus of claim 8 , wherein verifying that the at least one functional unit in the cryptographic processor is generating proper results comprises verifying that a hash unit in the cryptographic processor is generating correct hashes.

10. The apparatus of claim 8 , wherein verifying that the at least one functional unit in the cryptographic processor is generating proper results comprises verifying that a random number generator unit is generating random numbers.

11. The apparatus of claim 8 , wherein verifying that the at least one functional unit in the cryptographic processor is generating proper results comprises verifying that an exponential arithmetic unit or an arithmetic logic unit is computing proper results.