Methods of fabricating three dimensional semiconductor memory devices
A three dimensional semiconductor memory device has a stacked structure including cell gates stacked therein that are insulated from each other and first string selection gates laterally separated from each other, vertical active patterns extending through the first string selection gates, multi-layered dielectric layers between sidewalls of the vertical active patterns and the cell gates and between the sidewalls of the vertical active patterns and the first string selection gates, and at least one first supplement conductive pattern. The first string selection gates are disposed over an uppermost cell gate of the cell gates. Each vertical active pattern extends through each of the cell gates stacked under the first string selection gates. The first supplement conductive pattern is in contact with a sidewall of one of the first string selection gates.
1. A method of fabricating a three dimensional semiconductor memory, the method comprising:
forming a stack structure including sacrificial layers and insulating layers alternately stacked on a substrate;
forming a plurality of openings penetrating the stack structure to expose the substrate;
sequentially forming a vertical insulating layer and a vertical active pattern in each of the openings;
patterning the stack structure to form a mold structure including sacrificial patterns and insulating patterns alternately stacked on the substrate;
replacing the sacrificial patterns of the mold structure with gate patterns;
forming a cutting trench penetrating an uppermost gate pattern of the gate patterns to form selection gates laterally separated from each other; and
forming supplement conductive patterns on sidewalls of the selection gates exposed by the cutting trench.
2. The method as claimed in claim 1 , wherein the cutting trench is formed between the openings adjacent to each other.
3. The method as claimed in claim 1 , wherein the sidewalls of the selection gates are rounded.
4. The method as claimed in claim 1 , wherein forming the supplement conductive patterns includes:
laterally recessing sidewalls of the selection gates exposed by the cutting trench to form recess regions;
forming a supplement conductive layer on an inner wall of the cutting trench to fill the recessed regions, and
removing the supplement conductive layer outside the recessed regions.
5. The method as claimed in claim 1 , wherein forming the supplement conductive patterns includes:
laterally recessing sidewalls of the selection gates exposed by the cutting trench to form recess regions;
forming a supplement conductive layer on an inner wall of the cutting trench to fill the recessed regions, and
performing a selective growth process on the sidewalls of the selection gates exposed by the recessed regions as seed layers to form the supplement conductive patterns.
6. The method as claimed in claim 1 , wherein replacing the sacrificial patterns of the mold structure with gate patterns includes:
removing the sacrificial patterns to form gate regions between the insulating patterns, the gate regions exposing portions of the vertical insulating layer; and
forming the gate patterns in the gate regions.
7. The method as claimed in claim 6 , wherein replacing the sacrificial patterns of the mold structure with gate patterns further comprises forming a horizontal insulating layer in the gate regions before forming the gate patterns,
wherein the horizontal insulating layer horizontally extends from between the gate patterns and the vertical insulating layer to upper surfaces and lower surfaces of the gate patterns.
8. The method as claimed in claim 1 , wherein forming the mold structure includes forming trenches spaced apart from the openings and penetrating the stack structure to expose the substrate, the method further comprising:
forming device isolation patterns in the trenches to contact sidewalls of the gate patterns and the insulating patterns after forming the gate patterns.