IP Library Granted Patent US 9,048,865
Granted Patent B2
US 9,048,865 · App. 14/537,122 · Granted Jun 2, 2015

Conversion of a discrete time quantized signal into a continuous time, continuously variable signal

Inventor: Christopher Pagnanelli (Huntington Beach, CA)
Assignee: Syntropy Systems, LLC
H03M1/661H03F1/3247H03M3/30H03M1/747H04L27/04
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Quick Facts
Patent No.
US 9,048,865
App. No.
14/537,122
Granted
Jun 2, 2015
Kind
B2
Abstract

Provided are, among other things, systems, apparatuses, methods and techniques for converting a discrete-time quantized signal into a continuous-time, continuously variable signal. An exemplary converter preferably includes: (1) multiple oversampling converters, each processing a different frequency band, operated in parallel; (2) multirate (i.e., polyphase) delta-sigma modulators (preferably second-order or higher); (3) multi-bit quantizers; (4) multi-bit-to-variable-level signal converters, such as resistor ladder networks or current source networks; (5) adaptive nonlinear, bit-mapping to compensate for mismatches in the multi-bit-to-variable-level signal converters (e.g., by mimicking such mismatches and then shifting the resulting noise to a frequently range where it will be filtered out by a corresponding bandpass (reconstruction) filter); (6) multi-band (e.g., programmable noise-transfer-function response) bandpass delta-sigma modulators; and/or (7) a digital pre-distortion linearizer (DPL) for canceling noise and distortion introduced by an analog signal bandpass (reconstruction) filter bank.

Claims (22)

1. An apparatus for combining sub-rate outputs of a polyphase parallel processor into a single output, comprising:

a plurality of input lines for accepting sub-rate samples of an underlying full-rate input signal, the underlying full-rate input signal comprising a sequence of samples at a sampling rate or, correspondingly, said samples separated in time by a sampling period;

a plurality of delay elements coupled to the input lines; and

a signal combiner having inputs that are coupled to outputs of said delay elements and also having an output,

wherein the sub-rate samples on each of the plurality of said input lines are a sequence of values representing a different subsampling phase of the underlying full-rate input signal,

wherein said delay elements introduce different time-offsets in increments that are integer multiples of the sampling period of the underlying full-rate input signal,

wherein the signal combiner performs a summing operation, and

wherein said delay elements and said signal combiner together produce a filter response that includes a lowpass function having a bandwidth smaller than the sampling frequency of the underlying full-rate input signal.

2. An apparatus according to claim 1 , wherein said delay elements introduce offsets in time via resampling on different phases of a sub-rate clock.

3. The apparatus according to claim 1 , wherein said delay elements introduce offsets in time via signal propagation through delay lines.

4. The apparatus according to claim 3 , wherein said delay lines are entirely passive.

5. The apparatus according to claim 3 , wherein at least one of said delay lines is active.

6. The apparatus according to claim 1 , wherein there are a total of m delay elements, and values at the output of each said delay element reflect subsampling at a rate which is a factor of 1/m times the sampling frequency of the underlying full-rate input signal.

7. The apparatus according to claim 6 , wherein the lowpass function has a bandwidth that is approximately equal to 1/2·m times the sampling frequency of the underlying full-rate input signal.

8. The apparatus according to claim 7 , wherein a maximum frequency of the underlying full-rate input signal is approximately equal to 1/2·m times said sampling frequency.

9. The apparatus according to claim 1 , wherein said combiner performs continuous-time summation, and all discrete-time components of said apparatus operate at a maximum switching rate which is less than an effective sampling rate at the output of said combiner.

10. The apparatus according to claim 9 , wherein the effective sampling rate at the output of said combiner is equal to the sampling frequency of the underlying full-rate input signal.

11. The apparatus according to claim 1 , wherein the lowpass function has a bandwidth that is less than or equal to one-half of the sampling frequency of the underlying full-rate input signal.

12. The apparatus according to claim 11 , wherein a maximum frequency of the underlying full-rate input signal is less than or equal to one-half of said sampling frequency.

13. The apparatus according to claim 1 , wherein the lowpass function is approximately a sin c function.

14. The apparatus according to claim 1 , wherein a value of each of said sub-rate outputs is shaped according to a non-rectangular window, and the lowpass function has greater stopband attenuation than a sin c function.

15. The apparatus according to claim 1 , wherein the outputs of said delay elements are coupled to the inputs of said signal combiner and combined within said signal combiner without up-sampling.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2021
From: PAGNANELLI, CHRISTOPHER; SYNTROPY SYSTEMS, LLC
To: PAGNANELLI FAMILY TRUST
Reel/Frame 057998/0246 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2021
From: SYNTROPY SYSTEMS, LLC
To: PAGNANELLI, CHRISTOPHER
Reel/Frame 055928/0422 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2014
From: PAGNANELLI, CHRISTOPHER
To: SYNTROPY SYSTEMS, LLC
Reel/Frame 034136/0754 →
Continuity (9)
Continuation In Part 13647301 · Oct 8, 2012
Continuation 13400019 · Feb 17, 2012
Continuation In Part 12970379 · Dec 16, 2010
Provisional Application 61444643 · Feb 18, 2011
Provisional Application 61450617 · Mar 8, 2011
Provisional Application 61507568 · Jul 13, 2011
Provisional Application 61287079 · Dec 16, 2009
Provisional Application 61970846 · Mar 26, 2014
Related Publication 20150061911A1 · Mar 5, 2015