IP Library › Granted Patent US 9,049,394
Granted Patent B2
US 9,049,394 · App. 13/979,556 · Granted Jun 2, 2015

Solid imaging device

Inventors: Kazuki Fujita (Hamamatsu, JP); Ryuji Kyushima (Hamamatsu, JP); Harumichi Mori (Hamamatsu, JP)
Assignee: HAMAMATSU PHOTONICS K.K.
H04N5/3745H01L27/14658H04N5/374H04N5/357H04N5/378H01L27/14603H04N5/3532
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Quick Facts
Patent No.
US 9,049,394
App. No.
13/979,556
Granted
Jun 2, 2015
Kind
B2
Abstract

A solid-state imaging device includes a photodetecting section including pixels each including a transistor and a photodiode, readout wiring lines connected to the transistors, a signal output section for sequentially outputting voltage values according to the amounts of charges input through the respective readout wiring lines, potential change switches for switching the potentials of the readout wiring lines to a potential Vdr different from input potentials of integration circuits of the signal output section, and a controlling section. The controlling section switches potentials of the readout wiring lines to the different potential Vdr for a predetermined period included in a period, after an elapse of a readout period where voltage values corresponding to the amounts of charges generated in the pixels are sequentially output from the signal output section, until a next readout period is started.

Claims (15)

1. A solid-state imaging device comprising:

a photodetecting section having M×N (M is an integer not less than 2, N is an integer not less than 2) pixels each including a photodiode and a transistor connected at one end to the photodiode that are arrayed two-dimensionally in M rows and N columns;

N readout wiring lines arranged for each column, and connected to the-other-side ends of the transistors included in the pixels of corresponding columns;

a signal output section including N integration circuits for generating voltage values according to amounts of charges input through the respective N readout wiring lines, and for sequentially outputting voltage values output from the N integration circuits;

potential changing means for switching potentials of K (K is an integer not less than 1 and not more than N) readout wiring lines included in the N readout wiring lines to a potential different from input potentials of corresponding K integration circuits; and

a controlling section for controlling an output operation of voltage values in the signal output section and a switching operation of potentials in the potential changing means, wherein

the controlling section switches potentials of the K readout wiring lines to the different potential for a predetermined period included in a period, after an elapse of a readout period where voltage values corresponding to amounts of charges generated in the M×N pixels are sequentially output from the signal output section, until a next readout period is started.

2. The solid-state imaging device according to claim 1 , wherein the transistor includes a region made of at least one of polycrystalline silicon and amorphous silicon.

3. The solid-state imaging device according to claim 1 , wherein the potential changing means includes K switches provided between the K readout wiring lines and the K integration circuits, and the K switches selectively connect each of the K readout wiring lines to either one of a wiring line for supplying the different potential and each of the K integration circuits.

4. The solid-state imaging device according to claim 3 , wherein the K switches include a region made of monocrystalline silicon.

5. The solid-state imaging device according to claim 1 , wherein each of the K integration circuits includes a differential amplifier and a capacitive element connected between one input terminal and an output terminal of the differential amplifier,

the potential changing means includes a switch having first and second input terminals and an output terminal and for selectively connecting either of the first and second input terminals and the output terminal,

the output terminal is connected to the other input terminal of the differential amplifier,

the first input terminal is applied with a potential corresponding to the input potential, and

the second input terminal is applied with the different potential.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 12, 2013
From: FUJITA, KAZUKI; KYUSHIMA, RYUJI; MORI, HARUMICHI
To: HAMAMATSU PHOTONICS K.K.
Reel/Frame 030789/0574 →
Priority Claims (1)
JP 2011-007019 · Jan 17, 2011 · national
Continuity (1)
Related Publication 20130292549A1 · Nov 7, 2013