Circuit and method for improving sense amplifier reaction time in memory read operations
View Patent ↗A sense amplifier circuit, a method of modifying a differential voltage in a sense amplifier circuit and a memory system incorporating the sense amplifier circuit or the method are described. The sense amplifier circuit is described to include: (1) a differential amplifier having first and second inputs respectively couplable to first and second complimentary bit lines and configured to receive a differential voltage therefrom representing a current logic value to be read and (2) a sense speed alteration circuit having first and second outputs respectively coupled to the first and second inputs via respective first and second capacitors and configured to cause one of the first and second capacitors to discharge to increase the differential voltage when a previously read logic value is opposite the current logic value to be read.
1. A sense amplifier circuit, comprising:
a differential amplifier having first and second inputs respectively couplable to first and second complimentary bit lines and configured to receive a differential voltage therefrom representing a current logic value to be read; and
a sense speed alteration circuit having first and second outputs respectively coupled to said first and second inputs via respective first and second capacitors and configured to cause one of said first and second capacitors to discharge to increase said differential voltage across said inputs of said differential amplifier when a previously read logic value is opposite said current logic value to be read.
2. The sense amplifier circuit as recited in claim 1 wherein said sense speed alteration circuit is configured to employ a sense amplifier enable signal in causing said one of said first and second capacitors to discharge.
3. The sense amplifier circuit as recited in claim 2 wherein an output of said differential amplifier is coupled to a switch controlled by a signal based on said sense amplifier enable signal.
4. The sense amplifier circuit as recited in claim 2 wherein said first and second inputs are couplable to said first and second complimentary bit-lines via first and second switches, said first and second switches controlled by a signal based on said sense amplifier enable signal.
5. The sense amplifier circuit as recited in claim 2 wherein said sense speed alteration circuit includes:
a first NAND gate configured to employ said sense amplifier enable signal and said previously read logic value to provide said first output; and
a second NAND gate configured to employ said sense amplifier enable signal and a logical inverse of said previously read logic value.
6. The sense amplifier circuit as recited in claim 1 wherein said first and second capacitors are substantially equal in capacitance.
7. The sense amplifier circuit as recited in claim 1 wherein said first and second capacitors are embodied in MOS capacitors.
8. A method of modifying a differential voltage in a sense amplifier circuit, comprising:
charging first and second capacitors coupled to respective first and second inputs of a differential amplifier;
employing a memory cell containing a current logic value to be read to discharge one of the first and second complimentary bit-lines coupled respectively between said memory cell and said first and second inputs; and
discharging one of said pair of capacitors according to a previously read logic value to increase said differential voltage present across said input terminals of said differential amplifier when said previously read logic value is opposite said current logic value to be read.
9. The method as recited in claim 8 wherein said discharging comprises employing a sense amplifier enable signal.
10. The method as recited in claim 9 further comprising employing a signal based on said sense amplifier enable signal to control a switch coupled to an output of said differential amplifier.
11. The method as recited in claim 9 wherein said first and second inputs are couplable to said first and second complimentary bit-lines via first and second switches, said first and second switches, said method further comprising employing a signal based on said sense amplifier enable signal to control said switch.
12. The method as recited in claim 9 further comprising:
employing said sense amplifier enable signal and said previously read logic value to provide said first output; and
employing said sense amplifier enable signal and a logical inverse of said previously read logic value.
13. The method as recited in claim 8 wherein said first and second capacitors are substantially equal in capacitance.
14. The method as recited in claim 8 wherein said first and second capacitors are embodied in MOS capacitors.
15. A memory system, comprising:
an array of memory cells;
an addressing circuit configured to activate a memory cell of said array of memory cells and associated with a specified memory address; and
a sense amplifier circuit, including:
a differential amplifier having first and second inputs respectively couplable to first and second complimentary bit lines and configured to receive a differential voltage therefrom representing a current logic value to be read, and
a sense speed alteration circuit having first and second outputs respectively coupled to said first and second inputs via respective first and second transistors and configured to cause one of said first and second transistors to discharge to increase said differential voltage when a previously read logic value is opposite said current logic value to be read.
16. The memory system as recited in claim 15 wherein said sense speed alteration circuit is configured to employ a sense amplifier enable signal in causing said one of said first and second transistors to discharge.
17. The memory system as recited in claim 16 wherein an output of said differential amplifier is coupled to a switch controlled by a signal based on said sense amplifier enable signal.
18. The memory system as recited in claim 16 wherein said first and second inputs are couplable to said first and second complimentary bit-lines via first and second switches, said first and second switches controlled by a signal based on said sense amplifier enable signal.
19. The memory system as recited in claim 16 wherein said sense speed alteration circuit includes:
a first NAND gate configured to employ said sense amplifier enable signal and said previously read logic value to provide said first output; and
a second NAND gate configured to employ said sense amplifier enable signal and a logical inverse of said previously read logic value.
20. The memory system as recited in claim 15 wherein said first and second transistors are substantially equal in capacitance.
21. A sense amplifier circuit, comprising:
a differential amplifier having first and second inputs respectively couplable to first and second complimentary bit lines and configured to receive a differential voltage therefrom representing a current logic value to be read; and
a sense speed alteration circuit having first and second outputs respectively coupled to said first and second inputs via respective first and second transistors and configured to cause one of said first and second transistors to discharge to increase said differential voltage across said inputs of said differential amplifier when a previously read logic value is opposite said current logic value to be read.