Resistive memory device capable of preventing disturbance and method for manufacturing the same
A resistive memory device capable of preventing disturbance is provided. The resistive memory device includes a lower electrode formed on a semiconductor substrate, a variable resistor disposed on the lower electrode, an upper electrode disposed on the variable resistor, and an interlayer insulating layer configured to insulate the variable resistor. The interlayer insulating layer may include an air-gap area in at least a portion thereof.
1. A resistive memory device, comprising:
a lower electrode formed on a semiconductor substrate;
a first variable resistor disposed on the lower electrode;
a spacer surrounding an outer circumference of the variable resistor;
an upper electrode disposed on the variable resistor; and
an air-gap area adjacent to the first variable resistor and configured to insulate the first variable resistor,
wherein the upper electrode does not cover a top portion of the air gap.
2. The resistive memory device of claim 1 , further comprising a second variable resistor between a second lower electrode and a second upper electrode, wherein the air gap is disposed between the first and the second variable resistors.
3. The resistive memory device of claim 1 , further comprising a dielectric layer that overlies the air gap.
4. The resistive memory device of claim 3 , further comprising an encapsulation dielectric layer that covers the upper electrode covers a top portion of the air gap.
5. A method for manufacturing a resistive memory device, the method comprising:
forming a lower electrode on a semiconductor substrate;
forming an interlayer insulating layer having a variable resistor region to expose the lower electrode;
forming a first spacer on a sidewall of the variable resistor region;
forming a second spacer on a sidewall of the first spacer;
forming a variable resistor in the variable resistor region defined the second spacer;
removing the first spacer to form an air-gap area; and
forming an upper electrode on the variable resistor.
6. The method of claim 5 , wherein the upper electrode is formed to cover the second spacer, the air-gap area, and a portion of the interlayer insulating layer at an outer side of the air-gap area.
7. The method of claim 5 , wherein the first spacer includes a material having etch selectivity different from the second spacer and the interlayer insulating layer.
8. A method for manufacturing a resistive memory device, the method comprising:
forming a lower electrode on a semiconductor substrate;
forming an interlayer insulating layer having a variable resistor region to expose the lower electrode;
forming a first spacer on a sidewall of the variable resistor region;
forming a second spacer on a sidewall of the first spacer;
forming a variable resistor in the variable resistor region defined by the second spacer;
forming an upper electrode on the variable resistor;
recessing the expose interlayer insulating layer by a predetermined thickness using the upper electrode as a mask; and
removing at least one of the first spacer and the interlayer insulating layer to form an air-gap area.
9. The method of claim 8 , wherein the upper electrode is formed on the variable resistor, the second spacer, and the first spacer.
10. The method of claim 8 , wherein the first spacer includes a material having etch selectivity different from the second spacer and the interlayer insulating layer.
11. The method of claim 8 , wherein the first spacer includes a material having the same etch selectivity as the interlayer insulating layer.