Frequency divider
This disclosure relates to a divide-by-N frequency divider system and frequency dividing method. The system includes a ring oscillator having M stages, where M is an integer, and a zero mean current component coupled to one or more of the stages to provide a zero mean current flow path.
1. A divide-by-N frequency divider system, where N is an integer, comprising:
a ring oscillator having M stages, where M is an integer, the ring oscillator configured to receive an injection input signal and provide an output signal, and each of the M stages have a single input and a single output configured, respectively, to receive an output from its preceding stage in the ring and to provide an input to its succeeding stage in the ring; and
a zero mean current component coupled to one or more of the stages to provide a zero mean current flow path,
wherein each M stage comprises a Complementary Metal Oxide Semiconductor (CMOS) inverter and at least one transistor coupled between the CMOS inverter and the zero mean current component, the at least one transistor comprising a gate, source, and drain, the gate configured to receive an injection voltage, the source coupled to the zero mean current component, and the drain coupled to a node of the ring oscillator.
2. The divide-by-N frequency divider system according to claim 1 wherein the zero mean current component comprises one or more capacitors.
3. The divide-by-N frequency divider system according to claim 1 , wherein N is equal to M.
4. The divide-by-N frequency divider system according to claim 1 , wherein at least one of N or M is equal to 7.
5. The divide-by-N frequency divider system according to claim 1 , wherein N is an integer greater than 1 , and wherein each of the stages is coupled to a tail current source.
6. The divide-by-N frequency divider system according to claim 1 , wherein the output signal has a frequency equal to 1/N of the injection input signal to be divided, where M is different than N.
7. The divide-by-N frequency divider system according to claim 1 , wherein the output signal has a frequency equal to 1/N of the injection input signal to be divided, where M is equal to N.
8. The divide-by-N frequency divider system according to claim 1 further comprising at least one tail current source coupled to at least one stage of the ring oscillator.
9. A divide-by-N frequency divider system, where N is an integer, comprising:
a ring oscillator having M stages, where M is an integer, the ring oscillator configured to receive an injection input signal and provide an output signal; and
a zero mean current component coupled to one or more of the stages to provide a zero mean current flow path;
wherein the ring oscillator is a differential ring oscillator, and each of the M stages comprises:
a stage component having a first output terminal and a second output terminal:
a first injection device coupled between the first output terminal of the stage component and the zero mean current component; and
a second injection device coupled between the second output terminal of the stage component and the zero mean current component.
10. A frequency divider system comprising:
a plurality of stages, each stage including a stage component and an injection device coupled to the stage component; and
a zero mean current component coupled to the injection device to provide a zero mean current flow path;
wherein the stage component is a differential delay stage having a first output terminal and a second output terminal, and wherein the injection device is a first injection device coupled between the first output terminal of the stage component and the zero mean current component, the stage component further comprising a second injection device coupled between the second output terminal of the stage component and the zero mean current component.