Method and apparatus for timing synchronization at sub-sampled rate for sub-sampled wideband systems
A method of timing synchronization in sub-band based ultra wideband systems, includes obtaining a coarse estimate of an offset in a time domain at a sub-sampled rate, and obtaining a fine estimate of the offset in an analog domain. The method further includes correcting a timing in the analog domain by transforming the fine estimate to an equivalent phase for the correcting.
1. A method of timing synchronization in sub-band based ultra wideband systems, the method comprising:
obtaining, using a coarse estimation unit, a coarse estimate of an offset in a time domain at a sub-sampled rate, wherein the obtaining of the coarse estimate comprise performing, using the coarse estimation unit, cross correlation of a sub-sampled signal with a sub-sampled training sequence in a digital domain;
obtaining, using a fine estimation unit, a fine estimate of the offset in an analog domain; and
correcting, using a timing correction unit, a timing in the analog domain by transforming the fine estimate to an equivalent phase for the correcting.
2. The method as in claim 1 , wherein the method further comprises:
obtaining, using the coarse estimation unit, the coarse estimate for each sub-band based on a frequency diversity order of a user.
3. The method as in claim 2 , wherein the method further comprises:
obtaining, using the coarse estimation unit, a final coarse estimate of the offset from each sub-band by determining a maximum of estimates for a corresponding sub-band.
4. The method as in claim 3 , wherein the obtaining of the fine estimate comprises:
obtaining, using the fine estimation unit, the fine estimate in the analog domain based on the final coarse estimate.
5. The method as in claim 1 , wherein the obtaining of the fine estimate comprises:
performing, using the fine estimation unit, cross correlation of a delayed signal with a training sequence designed with a silence period.
6. The method as in claim 5 , wherein a length of the training sequence is equal to a number of orthogonal subcarriers present over a bandwidth of the delayed signal.
7. The method as in claim 5 , wherein the training sequence is an up-sampled version of a base training sequence.
8. The method as in claim 5 , wherein the training sequence of a sub-band is orthogonal up to a lag gap of an integer, the lag gap indicating a shift of sub-bands by a value of the integer.
9. The method as in claim 5 , wherein the training sequence is followed by the silence period of at least four orthogonal frequency division multiplexing symbols.
10. An apparatus configured to perform timing synchronization in sub-band based ultra wideband systems, the apparatus comprising:
a coarse estimation unit configured to obtain a coarse estimate of an offset in a time domain at a sub-sampled rate, wherein the coarse estimation unit is configured to
perform cross correlation of a sub-sampled signal with a sub-sampled training sequence in a digital domain;
a fine estimation unit configured to obtain a fine estimate of the offset in an analog domain; and
a timing correction unit configured to correct a timing in the analog domain by transforming the fine estimate to an equivalent phase for the correction.
11. The apparatus as in claim 10 , wherein the fine estimation unit is configured to:
perform cross correlation of a delayed signal with a training sequence designed with a silence period.
12. The apparatus as in claim 10 , further comprising:
a phase locked loop circuit configured to determine the equivalent phase based on the fine estimate;
an analog-to-digital converter configured to convert an input signal in the analog domain to a sub-sampled signal in a digital domain to be used to obtain the coarse estimate; and
an analog delay circuit configured to delay the input signal, the delayed input signal being used to obtain the fine estimate.
13. A receiver configured to perform timing synchronization in sub-band based ultra wideband systems, the receiver comprising:
a processor configured to
determine a first estimate of a timing offset of an input signal, in a digital domain, wherein the processor is configured to
sub-sample the input signal to generate a sub-sampled signal in the digital domain: and
perform cross correlation of the sub-sampled signal with a sub-sampled training sequence in the digital domain to generate the first estimate,
determine a second estimate of the timing offset in an analog domain based on the first estimate, and
determine an equivalent phase to be used to correct a timing of the input signal, based on the second estimate.
14. The receiver as in claim 13 , wherein the processor is further configured to:
scale the first estimate; and
determine the second estimate based on the scaled first estimate.
15. The receiver as in claim 13 , wherein the processor is configured to:
delay the input signal; and
perform cross correlation of the delayed input signal with a training sequence followed by a silence period, based on the first estimate, to generate a correlated output.
16. The receiver as in claim 15 , wherein the processor is configured to:
determine the second estimate to be the same value as the first estimate in response to the correlated output being greater than or equal to a predetermined threshold.
17. The receiver as in claim 13 , wherein the processor is configured to:
control a switching of an analog-to-converter clock from an initial phase to the equivalent phase based on a predetermined timing delay, to correct the timing of the input signal.