Adaptive equalization using correlation of edge samples with data patterns
An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data clock signals to note the locations of zero crossings for one or more selected data patterns. The pattern or patterns may be selected from among those apt to produce the greatest timing error. Equalization settings may then be adjusted to align the zero crossings of the selected data patterns with the recovered edge clock signal.
1. A receiver comprising:
an equalizer to issue an equalized data signal responsive to an input data signal;
a data sampler to sample the equalized data signal on edges of a data-clock signal, thereby generating a series of samples;
clock-recovery circuitry to recover the data-clock signal responsive to the samples; and
equalizer control circuitry to receive the samples, the equalizer control circuitry to adjust the equalizer responsive to a specific pattern of the samples, the specific pattern including successive first bit values followed by a transition to a second bit value.
2. The receiver of claim 1 , the equalizer control circuitry including memory to store the specific pattern.
3. The receiver of claim 2 , the memory to store the specific pattern and at least one additional pattern, the equalizer control circuitry adjust the equalizer responsive to the specific pattern and the at least one additional pattern.
4. The receiver of claim 1 , the equalizer control circuitry further having an edge sampler to sample at least one of the input data signal and the equalized data signal to produce edge samples and a phase detector to generate an timing signal responsive to the edge samples with the data samples.
5. The receiver of claim 4 , the equalizer control circuitry to adjust the equalizer responsive to the specific pattern and the timing signal.
6. The receiver of claim 1 , the equalizer control circuitry including a correlator to issue a match signal responsive to the specific pattern.
7. The receiver of claim 1 , wherein the equalizer exhibits a frequency-dependent first amplification factor and a frequency-dependent second amplification factor, and the equalizer control circuitry adjusts relative values of the first amplification factor and the second amplification factor.
8. A method comprising:
receiving an input data signal;
equalizing the input data signal to create an equalized signal;
sampling the equalized signal on edges of a clock signal to generate a series of data samples, each data sample representing one of a first value and a second value;
adjusting the clock signal responsive to the data samples; and
adjusting the equalizing responsive to a specific pattern of the data samples, the specific pattern including successive bits of the first value followed by a transition to a bit of the second value.
9. The method of claim 8 , further comprising receiving and loading the specific pattern.
10. The method of claim 8 , further comprising adjusting the equalizing responsive to a second specific pattern of the samples.
11. The method of claim 8 , further comprising sampling an edge of at least one of the input data signal and the equalized signal to obtain edge samples, and adjusting the equalizer responsive to the edge samples.
12. The method of claim 11 , further comprising adjusting the equalizer responsive to the data samples.
13. The method of claim 8 , wherein the specific pattern includes a second transition to the first value exactly one bit after the transition to the bit of the second value.
14. A receiver comprising:
an equalizer to issue an equalized data signal responsive to an input data signal;
a data sampler to sample the equalized data signal on edges of a data-clock signal, thereby generating a series of data samples;
means for recovering the data-clock signal responsive to the samples; and
means for controlling the equalizer responsive to a specific pattern of the data samples, the specific pattern including successive first bit values followed by a transition to a second bit value.
15. The receiver of claim 14 , further comprising memory to load with the specific pattern.
16. The receiver of claim 15 , the memory to store the specific pattern and at least one additional pattern, the means for controlling the equalizer to adjust the equalizer responsive to the specific pattern and the at least one additional pattern.
17. The receiver of claim 14 , further comprising means for recovering a clock signal from at least one of the input data signal and the equalized signal, the data sampler to sample the input data signal timed to the clock signal.
18. The receiver of claim 14 , further comprising an edge sampler to sample edges of at least one of the equalized data signal and the input data signal, wherein the means for controlling the equalizer controls the equalizer responsive to the sampled edges.
19. The receiver of claim 18 , wherein the means for controlling the equalizer controls the equalizer responsive to the data samples.