Memory protection cache

1. A system for accessing data at a memory, comprising:

a processor configured to:

receive a request associated with an operation, wherein the request includes a logical address associated with the memory;

determine a type of access associated with the request based at least in part on the logical address;

generate a physical address based at least in part on (1) the type of access and (2) the logical address, wherein to generate the physical address based at least in part on (1) the type of access and (2) the logical address includes to:

in the even that the type of access comprises a first type of access, generate the physical address based at least in part on translating the logical address; and

in the event that the type of access comprises a second type of access, generate the physical address based at least in part on not translating the logical address;

determine a block of data at the memory that includes data associated with the physical address; and

access data at the block of data and a corresponding set of ECC from the memory based at least in part on the type of access; and

the memory coupled to the processor and configured to provide the processor with instructions.

2. The system of claim 1 , wherein to access data at the determined block of data and the corresponding set of ECC from the memory based at least in part on the type of access includes to:

in the event that the type of access comprises the first type of access, determine whether the accessed data can be decoded based at least in part on the corresponding set of ECC; and

in the event that the type of access comprises the second type of access, return the data associated with the determined block of data and the corresponding set of ECC.

3. The system of claim 2 , wherein in the even that the type of access comprises the first type of access and in the event that the accessed data can be decoded, the processor is further configured to store the accessed data at a corresponding cache.

4. The system of claim 3 , wherein in the event the operation comprises a write operation, the processor is further configured to:

update the accessed data stored at the corresponding cache based at least in part on the request; and

indicate that the update block of data stored at the corresponding cache is dirty.

5. The system of claim 4 , wherein the processor is further configured to:

generate a new set of ECC corresponding to the updated block of data; and

write back data associated with the updated block of data and also the corresponding new set of ECC to the memory.

6. The system of claim 1 , wherein a physical address of the corresponding set of ECC is sequential to a physical address associated with the block of data.

7. The system of claim 1 , wherein a physical address of the corresponding set of ECC is not sequential to a physical address associated with the block of data.

8. The system of claim 1 , wherein the block of data comprises a cache line.

9. The system of claim 1 , wherein to determine the block of data includes to determine a start physical address and an end physical address associated with the block of data.

10. The system of claim 1 , wherein to determine the block of data includes to determine a range of physical addresses associated with the block of data.

11. A method for accessing data at a memory, comprising:

receiving a request associated with an operation, wherein the request includes a logical address associated with the memory;

determining a type of access associated with the request based at least in part on the logical address;

generating a physical address based at least in part on (1) the type of access and (2) the logical address, wherein generating the physical address based at least in part on (1) the type of access and (2) the logical address includes:

in the event that the type of access comprises a first type of access, generating the physical address based at least in part on translating the logical address; and

in the event that the type of access comprises a second type of access, generating the physical address based at least in part on not translating the logical address;

determining a block of data at the memory that includes data associated with the physical address; and

accessing data at the block of data and a corresponding set of ECC from the memory based at least in part on the type of access.

12. The method of claim 11 , wherein accessing data at the determined block of data and the corresponding set of ECC from the memory based at least in part on the type of access includes:

in the event that the type of access comprises the first type of access, determining whether the accessed data can be decoded based at least in part on the corresponding set of ECC; and

in the event that the type of access comprises the second type of access, returning the data associated with the determined block of data and the corresponding set of ECC.

13. The method of claim 12 , wherein in the event that the type of access comprises the first type of access and in the event that the accessed data can be decoded, further comprising storing the accessed data at a corresponding cache.

14. The method of claim 13 , wherein in the event the operation comprises a write operation, further comprising:

updating the accessed data stored at the corresponding cache based at least in part on the request; and

indicating that the updated block of data stored at the corresponding cache is dirty.

15. The method of claim 14 , further comprising:

generating a new set of ECC corresponding to the updated block of data; and

writing back data associated with the updated block of data and also the corresponding new set of ECC to the memory.

16. The method of claim 11 , wherein the block of data comprises a cache line.

17. A computer program product for accessing data at a memory, the computer program product being embodied in a non transitory computer readable storage medium and comprising computer instructions for:

receiving a request associated with an operation, wherein the request includes a logical address associated with the memory;

determining a type of access associated with the request based at least in part on the logical address;

generating a physical address based at least in part on (1) the type of access and (2) the logical address, wherein generating the physical address based at least in part on (1) the type of access and (2) the logical address includes:

in the event that the type of access comprises a first type of access, generating the physical address based at least in part on translating the logical address; and

in the event that the type of access comprises a second type of access, generating the physical address based at least in part on not translating the logical address;

determining a block of data at the memory that includes data associated with the physical address; and

accessing data at the block of data and a corresponding set of ECC from the memory based at least in part on the type of access.