IP Library › Granted Patent US 9,058,889
Granted Patent B2
US 9,058,889 · App. 13/937,559 · Granted Jun 16, 2015

Pulse output circuit, display device, and electronic device

Inventor: Hiroyuki Miyake (Ebina, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
G11C19/188G09G2310/0286G11C19/184G11C19/28
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Quick Facts
Patent No.
US 9,058,889
App. No.
13/937,559
Granted
Jun 16, 2015
Kind
B2
Abstract

An object is to suppress the stress applied to a transistor as well as suppressing generation of defective operation. In a pulse output circuit having a function of outputting a pulse signal and including a transistor that controls whether to set the pulse signal to high level, in a period during which the pulse signal output from the pulse output circuit is at low level, the potential of a gate of a transistor is not set to a constant value but intermittently set to a value higher than the potential VSS. Accordingly, the stress to the transistor can be suppressed.

Claims (66)

1. A pulse output circuit comprising:

a first transistor, one of a source and a drain of the first transistor being electrically connected to a first wiring to which a first clock signal is supplied;

a second transistor, one of a source and a drain of the second transistor being electrically connected to the other of the source and the drain of the first transistor, and the other of the source and the drain of the second transistor being electrically connected to a second wiring to which a first potential is supplied;

a third transistor, a gate of the third transistor being electrically connected to a third wiring to which a second clock signal is supplied, one of a source and a drain of the third transistor being electrically connected to a gate of the first transistor, and the other of the source and the drain of the third transistor being electrically connected to a fourth wiring to which a second potential is supplied;

a fourth transistor, a gate of the fourth transistor being electrically connected to a fifth wiring to which a third clock signal is supplied, and one of a source and a drain of the fourth transistor being electrically connected to the gate of the first transistor; and

a fifth transistor, a gate of the fifth transistor being electrically connected to a sixth wiring to which a reset signal is supplied, one of a source and a drain of the fifth transistor being electrically connected to the gate of the second transistor, and the other of the source and the drain of the fifth transistor being electrically connected to a seventh wiring to which a third potential is supplied,

wherein a potential of the gate of the first transistor is configured to be changed by the third transistor and the fourth transistor in accordance with the second clock signal and the third clock signal in a period during the pulse output circuit outputs a low-level signal.

2. The pulse output circuit according to claim 1 , further comprising a capacitor,

wherein one electrode of the capacitor is electrically connected to the gate of the first transistor, and

wherein the other electrode of the capacitor is electrically connected to the other of the source and the drain of the first transistor.

3. The pulse output circuit according to claim 1 , further comprising a sixth transistor,

wherein a gate of the sixth transistor is electrically connected to an eighth wiring to which a set signal is supplied,

wherein one of a source and a drain of the sixth transistor is electrically connected to the other of the source and the drain of the fourth transistor, and

wherein the other of the source and the drain of the sixth transistor is electrically connected to the seventh wiring to which the third potential is supplied.

4. The pulse output circuit according to claim 1 , further comprising a seventh transistor,

wherein a gate of the seventh transistor is electrically connected to an eighth wiring to which a set signal is supplied,

wherein one of a source and a drain of the seventh transistor is electrically connected to the gate of the second transistor, and

wherein the other of the source and the drain of the seventh transistor is electrically connected to the second wiring to which the second potential is supplied.

5. The pulse output circuit according to claim 1 ,

wherein the pulse output circuit is configured to output a high-level signal or the low-level signal from the other of the source and the drain of the first transistor, in accordance with the first clock signal, the second clock signal, and the third clock signal.

6. The pulse output circuit according to claim 1 ,

wherein a difference between the second potential and the first potential is larger than a threshold voltage of the first transistor.

7. The pulse output circuit according to claim 1 ,

wherein a channel formation region of each of the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor comprises an oxide semiconductor.

8. A display device comprising the pulse output circuit according to claim 1 .

9. A pulse output circuit comprising:

a first transistor, one of a source and a drain of the first transistor being electrically connected to a first wiring to which a first clock signal is supplied;

a second transistor, one of a source and a drain of the second transistor being electrically connected to the other of the source and the drain of the first transistor, and the other of the source and the drain of the second transistor being electrically connected to a second wiring to which a first potential is supplied;

a third transistor, a gate of the third transistor being electrically connected to a third wiring to which a second clock signal is supplied, one of a source and a drain of the third transistor being electrically connected to a gate of the first transistor, and the other of the source and the drain of the third transistor being electrically connected to a fourth wiring to which a second potential is supplied;

a fourth transistor, a gate of the fourth transistor being electrically connected to a fifth wiring to which a third clock signal is supplied, and one of a source and a drain of the fourth transistor being electrically connected to the gate of the first transistor; and

a fifth transistor, a gate of the fifth transistor being electrically connected to a sixth wiring to which a reset signal is supplied, one of a source and a drain of the fifth transistor being electrically connected to the gate of the second transistor, and the other of the source and the drain of the fifth transistor being electrically connected to a seventh wiring to which a third potential is supplied,

wherein a potential of the gate of the first transistor is configured to be set to the second potential by turning on the third transistor and turning off the fourth transistor in accordance with the second clock signal and the third clock signal in a period during the pulse output circuit outputs a low-level signal.

10. The pulse output circuit according to claim 9 , further comprising a capacitor,

wherein one electrode of the capacitor is electrically connected to the gate of the first transistor, and

wherein the other electrode of the capacitor is electrically connected to the other of the source and the drain of the first transistor.

11. The pulse output circuit according to claim 9 , further comprising a sixth transistor,

wherein a gate of the sixth transistor is electrically connected to a sixth an eighth wiring to which a set signal is supplied,

wherein one of a source and a drain of the sixth transistor is electrically connected to the other of the source and the drain of the fourth transistor, and

wherein the other of the source and the drain of the sixth transistor is electrically connected to the seventh wiring to which the third potential is supplied.

12. The pulse output circuit according to claim 9 , further comprising a seventh transistor,

wherein a gate of the seventh transistor is electrically connected to an eighth wiring to which a set signal is supplied,

wherein one of a source and a drain of the seventh transistor is electrically connected to the gate of the second transistor, and

wherein the other of the source and the drain of the seventh transistor is electrically connected to the second wiring to which the second potential is supplied.

13. The pulse output circuit according to claim 9 ,

wherein the pulse output circuit is configured to output a high-level signal or the low-level signal from the other of the source and the drain of the first transistor, in accordance with the first clock signal, the second clock signal, and the third clock signal.

14. The pulse output circuit according to claim 9 ,

wherein a difference between the second potential and the first potential is larger than a threshold voltage of the first transistor.

15. The pulse output circuit according to claim 9 ,

wherein a channel formation region of each of the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor comprises an oxide semiconductor.

16. A display device comprising the pulse output circuit according to claim 9 .

17. A pulse output circuit comprising:

a first transistor, one of a source and a drain of the first transistor being electrically connected to a first wiring to which a first clock signal is supplied;

a second transistor, one of a source and a drain of the second transistor being electrically connected to the other of the source and the drain of the first transistor, and the other of the source and the drain of the second transistor being electrically connected to a second wiring to which a first potential is supplied;

a third transistor, a gate of the third transistor being electrically connected to a third wiring to which a second clock signal is supplied, one of a source and a drain of the third transistor being electrically connected to a gate of the first transistor, and the other of the source and the drain of the third transistor being electrically connected to a fourth wiring to which a second potential is supplied;

a fourth transistor, a gate of the fourth transistor being electrically connected to a fifth wiring to which a third clock signal is supplied, and one of a source and a drain of the fourth transistor being electrically connected to the gate of the first transistor; and

a fifth transistor, a gate of the fifth transistor being electrically connected to a sixth wiring to which a reset signal is supplied, one of a source and a drain of the fifth transistor being electrically connected to the gate of the second transistor, and the other of the source and the drain of the fifth transistor being electrically connected to a seventh wiring to which a third potential is supplied.

18. The pulse output circuit according to claim 17 , further comprising a sixth transistor,

wherein a gate of the sixth transistor is electrically connected to an eighth wiring to which a set signal is supplied,

wherein one of a source and a drain of the sixth transistor is electrically connected to the other of the source and the drain of the fourth transistor, and

wherein the other of the source and the drain of the sixth transistor is electrically connected to the seventh wiring to which the third potential is supplied.

19. The pulse output circuit according to claim 17 , further comprising a seventh transistor,

wherein a gate of the seventh transistor is electrically connected to an eighth wiring to which a set signal is supplied,

wherein one of a source and a drain of the seventh transistor is electrically connected to the gate of the second transistor, and

wherein the other of the source and the drain of the seventh transistor is electrically connected to the second wiring to which the second potential is supplied.

20. The pulse output circuit according to claim 17 ,

wherein a channel formation region of each of the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor comprises an oxide semiconductor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 9, 2013
From: MIYAKE, HIROYUKI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 030759/0346 →
Priority Claims (1)
JP 2012-161253 · Jul 20, 2012 · national
Continuity (1)
Related Publication 20140023173A1 · Jan 23, 2014