Lateral silicon-on-insulator bipolar junction transistor process and structure
Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first terminal of the bipolar junction transistor is formed from a section of a device layer of a semiconductor-on-insulator wafer. An intrinsic base of the bipolar junction transistor is formed from an epitaxially-grown section of a first semiconductor layer, which is coextensive with a sidewall of the section of the device layer. A second terminal of the bipolar junction transistor is formed from a second semiconductor layer that is coextensive with the epitaxially-grown section of the first semiconductor layer. The epitaxially-grown section of a first semiconductor layer defines a first junction with the section of the device layer, and the second semiconductor layer defines a second junction with the epitaxially-grown section of the first semiconductor layer.
1. A method of fabricating a device structure for a bipolar junction transistor, the method comprising:
patterning a device layer of a semiconductor-on-insulator wafer to form a section of the device layer;
epitaxially growing a first section of a first semiconductor layer that is coextensive with a sidewall of the section of the device layer to form a first junction; and
forming a second semiconductor layer that is coextensive with the first semiconductor layer to form a second junction,
wherein the section of the device layer defines a first terminal of the bipolar junction transistor, the first semiconductor layer defines an intrinsic base of the bipolar junction transistor, and the second semiconductor layer defines a second terminal of the bipolar junction transistor.
2. The method of claim 1 wherein forming the second semiconductor layer that is coextensive with the first semiconductor layer comprises:
epitaxially growing a single crystal section of the second semiconductor layer on the first section of the first semiconductor layer.
3. The method of claim 2 wherein the epitaxial growth of the single crystal section of the second semiconductor layer is in a lateral direction relative to the sidewall of the section of the device layer.
4. The method of claim 1 further comprising:
before the first semiconductor layer is epitaxially grown, recessing a top surface of a buried insulator layer of the semiconductor-on-insulator wafer relative to the section of the device layer at a location adjacent to the sidewall.
5. The method of claim 4 wherein a second section of the first semiconductor layer extends below the section of the device layer toward the top surface of the buried insulator layer.
6. The method of claim 1 further comprising:
depositing a first dielectric layer on a top surface of the device layer; and
depositing a third semiconductor layer on the first dielectric layer,
wherein the first dielectric layer and the third semiconductor layer are patterned when the device layer is patterned.
7. The method of claim 6 wherein the first semiconductor layer has a second section that is integral with the first section and that extends across the first dielectric layer to couple the first section of the first semiconductor layer with the third semiconductor layer.
8. The method of claim 6 further comprising:
depositing a second dielectric layer on a top surface of the third semiconductor layer;
patterning the second dielectric layer to define a hardmask that is used to pattern the third semiconductor layer, the first dielectric layer, and the device layer;
forming a first opening in the second dielectric layer that extends to the third semiconductor layer; and
forming a first contact inside the first opening that is coupled with the intrinsic base.
9. The method of claim 8 further comprising:
forming a second opening in the third semiconductor layer and the first dielectric layer that coincides with the first opening and that extends to the device layer; and
forming a second contact inside the second opening that is coupled with the first terminal,
wherein the second opening is smaller than the first opening.
10. The method of claim 1 wherein the epitaxial growth of the first section of the first semiconductor layer is in a lateral direction relative to the sidewall of the section of the device layer.