Bi-directional ESD diode structure with ultra-low capacitance that consumes a small amount of silicon real estate
A bi-directional electrostatic discharge diode structure consumes substantially less silicon real estate and provides ultra-low capacitance by utilizing a p− epitaxial layer that touches and lies between an n+ lower epitaxial layer and an n+ upper epitaxial layer. A metal contact touches and lies over a p+ layer, which touches and lies over the n+ upper epitaxial layer.
1. A diode structure comprising:
a substrate region of a first conductivity type, the substrate region having a dopant concentration;
a first semiconductor layer of a second conductivity type, the first semiconductor layer having a dopant concentration, and touching and lying over the substrate region;
a second semiconductor layer of the first conductivity type, the second semiconductor layer touching and lying over the first semiconductor layer, the second semiconductor layer having a dopant concentration that is substantially less than the dopant concentration of the substrate region;
a third semiconductor layer of the second conductivity type, the third semiconductor layer touching and lying over the second semiconductor layer; and
a fourth semiconductor layer of the first conductivity type, the fourth semiconductor touching and lying over the third semiconductor layer, wherein:
the second semiconductor layer lies completely between the first semiconductor layer and the third semiconductor layer; and
the third semiconductor layer lies completely between the second semiconductor layer and the fourth semiconductor layer.
2. The diode structure of claim 1 wherein the third semiconductor layer has a dopant concentration substantially equal to the dopant concentration of the first semiconductor layer.
3. The diode structure of claim 2 wherein the fourth semiconductor layer has a dopant concentration substantially equal to the dopant concentration of the substrate region.
4. The diode structure of claim 3 and further comprising a metal contact that touches and lies over the fourth semiconductor layer.
5. The diode structure of claim 1 and further comprising a trench isolation structure that touches and laterally surrounds a portion of the substrate region, the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer.
6. The diode structure of claim 5 wherein the trench isolation structure includes a polycrystalline silicon core and an isolation structure that lies between the polycrystalline silicon core and the substrate region.
7. The diode structure of claim 5 and further comprising:
a first non-conductive layer that touches and lies over the fourth semiconductor layer; and
a second non-conductive layer that touches and lies over the first non-conductive layer.
8. The diode structure of claim 7 wherein the metal contact touches and lies over a portion of the first non-conductive layer.
9. A bidirectional ESD diode structure comprising:
a top diode, the top diode including a first p+ region touching and overlying a first n+ epitaxial layer, the first p+ region forming an anode;
a bottom diode, the bottom diode including a second n+ epitaxial layer touching and overlying a p+ substrate region;
a p− epitaxial layer between the top diode and the bottom diode, wherein the p− epitaxial layer separates the first n+ epitaxial layer from the second n+ epitaxial layer; and
a metal contact in contact with the anode.
10. The bidirectional ESD diode structure of claim 9 wherein the first n+ epitaxial layer has a dopant concentration substantially equal to the dopant concentration of the second n+ epitaxial layer.
11. The bidirectional ESD diode structure of claim 10 wherein the first p+ region has a dopant concentration substantially equal to the dopant concentration of the p+ substrate region.
12. The bidirectional ESD diode structure of claim 11 wherein the p− epitaxial layer lies completely between the second n+ epitaxial layer and the first n+ epitaxial layer.
13. The bidirectional ESD diode structure of claim 12 wherein the first n+ epitaxial layer lies completely between the p− epitaxial layer and the first p+ region.
14. The bidirectional ESD diode structure of claim 13 and further comprising a trench isolation structure that touches and laterally surrounds a portion of the p+ substrate region, the second n+ epitaxial layer, p− epitaxial layer, first n+ epitaxial layer, and the first p+ region.
15. The bidirectional ESD diode structure of claim 14 wherein the trench isolation structure includes a polycrystalline silicon core and an isolation structure that lies between the polycrystalline silicon core and the p+ substrate region.