Solid-state imaging device, method of driving a solid-state imaging device, and electronic apparatus including a solid-state imaging device
A solid-state imaging device includes a first chip including a plurality of pixels, each pixel including a light sensing unit generating a signal charge responsive to an amount of received light, and a plurality of MOS transistors reading the signal charge generated by the light sensing unit and outputting the read signal charge as a pixel signal, a second chip including a plurality of pixel drive circuits supplying desired drive pulses to pixels, the second chip being laminated beneath the first chip in a manner such that the pixel drive circuits are arranged beneath the pixels formed in the first chip to drive the pixels, and a connection unit for electrically connecting the pixels to the pixel drive circuits arranged beneath the pixels.
1. A solid-state imaging device, comprising:
a first chip including a cyclic layout pattern circuit having unit circuits cyclically arranged in a regular pattern in at least one of a row direction along which rows of pixels of a pixel array having a matrix of rows and columns of pixels, each pixel including a photoelectric converter, are arranged, and a column direction along which columns of pixels of the pixel array are arranged;
a second chip laminated on the first chip, the second chip including an adjustment circuit for adjusting individually a timing of a signal of each unit circuit of the cyclic layout pattern circuit, the adjustment circuit including a storage unit and a plurality of unit circuits corresponding to the unit circuits of the cyclic layout pattern circuit; and
a connection unit, having a three-dimensional connection structure, for electrically connecting each unit circuit of the cyclic layout pattern on the first chip to each unit circuit of the adjustment circuit on the second chip in a mapped relationship.
2. The solid-state imaging device according to claim 1 , having a shutter function that is performed concurrently on all the pixels, and
wherein the cyclic layout pattern circuit comprises a row scanning unit for outputting a pixel drive signal driving each pixel of the pixel array, the row scanning unit concurrently outputting the pixel drive signals to all the pixel rows when the shutter function is concurrently performed on all the pixels.
3. The solid-state imaging device according to claim 2 , wherein the adjustment circuit sets the pixel drive signals output from the unit circuits of the row scanning unit to be concurrent by adjusting timings of the pixel drive signals.
4. The solid-state imaging device according to claim 1 , wherein the adjustment circuit comprises as the plurality of unit circuits a plurality of variable delay circuits, each variable delay circuit varying a delay amount thereof.
5. The solid-state imaging device according to claim 4 , wherein the variable delay circuits and the storage unit are arranged on different chips, and
wherein the chip having the variable delay circuits and the chip having the storage unit are electrically connected by a three-dimensional connection.
6. The solid-state imaging device according to claim 4 , wherein the adjustment circuit adjusts timings of the signals of the unit circuit of the cyclic layout pattern circuit by adjusting the delay amount of the plurality of variable delay circuits in response to a predictive value pre-stored on the storage unit.
7. The solid-state imaging device according to claim 1 , wherein the cyclic layout pattern circuit is arranged in a chip different from the chip having the pixel array, and the chip having the cyclic layout pattern circuit is laminated on the chip having the pixel array.
8. The solid-state imaging device according to claim 7 , wherein the cyclic layout pattern circuit includes the plurality of unit circuits, each unit circuit supporting one column of pixels or a plurality of columns of pixels in the pixel array on a one-to-one correspondence basis and wherein the plurality of unit circuits are respectively electrically connected to the one column of pixels or the plurality of columns of pixels in the pixel array by a three-dimensional connection.
9. The solid-state imaging device according to claim 8 , wherein the adjustment circuit comprises the plurality of unit circuits, each unit circuit supporting one unit circuit or a plurality of unit circuits of the cyclic layout pattern circuit on a one-to-one correspondence basis, and the plurality of unit circuits are respectively electrically connected to the one unit circuit or the plurality of unit circuits of the cyclic layout pattern circuit by a three-dimensional connection.
10. A method of driving a solid-state imaging device, the solid-state imaging device including a first chip including a cyclic layout pattern circuit having unit circuits cyclically arranged in a regular pattern in at least one of a row direction along which rows of pixels of a pixel array having a matrix of rows and columns of pixels, each pixel including a photoelectric converter, are arranged, and a column direction along which columns of pixels of the pixel array are arranged, a second chip laminated on the first chip, the second chip including an adjustment circuit, the adjustment circuit including a storage unit and a plurality of unit circuits corresponding to the unit circuits of the cyclic layout pattern circuit, and a connection unit for electrically connecting each unit circuit of the cyclic layout pattern on the first chip to each unit circuit of the adjustment circuit on the second chip in a mapped relationship,
the method comprising adjusting a timing of a signal of each unit circuit of the cyclic layout pattern circuit on a per unit circuit basis of the adjustment circuit.
11. An electronic apparatus comprising a solid-state imaging device, the solid-state imaging device including:
a first chip including a cyclic layout pattern circuit having unit circuits cyclically arranged in a regular pattern in at least one of: 1) a row direction along which rows of pixels of a pixel array having a matrix of rows and columns of pixels run, wherein each pixel includes a photoelectric converter, and 2) a column direction along which columns of pixels of the pixel array run;
a second chip laminated on the first chip, the second chip including an adjustment circuit for adjusting individually a timing of a signal of each unit circuit included in the cyclic layout pattern circuit, the adjustment circuit including a storage unit and a plurality of unit circuits corresponding to the unit circuits included in the cyclic layout pattern circuit; and
a connection unit for electrically connecting each unit circuit included in the cyclic layout pattern to each unit circuit included in the adjustment circuit in a mapped relationship.
12. The electronic apparatus according to claim 11 , having a shutter function that is performed concurrently on all the pixels, and
wherein the cyclic layout pattern circuit comprises a row scanning unit for outputting a pixel drive signal driving each pixel of the pixel array, the row scanning unit concurrently outputting the pixel drive signals to all the pixel rows when the shutter function is concurrently performed on all the pixels.
13. The electronic apparatus according to claim 12 , wherein the adjustment circuit sets the pixel drive signals output from the unit circuits of the row scanning unit to be concurrent by adjusting timings of the pixel drive signals.
14. The electronic apparatus according to claim 11 , wherein the adjustment circuit comprises as the plurality of unit circuits a plurality of variable delay circuits, each variable delay circuit varying a delay amount thereof.
15. The electronic apparatus according to claim 14 , wherein the variable delay circuits and the storage unit are arranged on different chips, and
wherein the chip having the variable delay circuits and the chip having the storage unit are electrically connected by a three-dimensional connection.
16. The electronic apparatus according to claim 14 , wherein the adjustment circuit adjusts timings of the signals of the unit circuit of the cyclic layout pattern circuit by adjusting the delay amount of the plurality of variable delay circuits in response to a predictive value pre-stored on the storage unit.
17. The electronic apparatus according to claim 11 , wherein the cyclic layout pattern circuit is arranged in a chip different from the chip having the pixel array, and the chip having the cyclic layout pattern circuit is laminated on the chip having the pixel array.
18. The electronic apparatus according to claim 17 , wherein the cyclic layout pattern circuit includes the plurality of unit circuits, each unit circuit supporting one column of pixels or a plurality of columns of pixels in the pixel array on a one-to-one correspondence basis and wherein the plurality of unit circuits are respectively electrically connected to the one column of pixels or the plurality of columns of pixels in the pixel array by a three-dimensional connection.
19. The electronic apparatus according to claim 18 , wherein the adjustment circuit comprises the plurality of unit circuits, each unit circuit supporting one unit circuit or a plurality of unit circuits of the cyclic layout pattern circuit on a one-to-one correspondence basis, and the plurality of unit circuits are respectively electrically connected to the one unit circuit or the plurality of unit circuits of the cyclic layout pattern circuit by a three-dimensional connection.