IP Library › Granted Patent US 9,064,814
Granted Patent B2
US 9,064,814 · App. 13/921,221 · Granted Jun 23, 2015

Semiconductor structure having metal gate and manufacturing method thereof

Inventors: Yi-Ching Wu (Kaohsiung, TW); Chih-Sen Huang (Tainan, TW); Ching-Wen Hung (Tainan, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L21/311H01L23/485H01L21/823842
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Quick Facts
Patent No.
US 9,064,814
App. No.
13/921,221
Granted
Jun 23, 2015
Kind
B2
Abstract

A manufacturing method for a semiconductor device first provides a substrate having at least a first transistor formed thereon. The first transistor includes a first conductivity type. The first transistor further includes a first metal gate and a protecting layer covering sidewalls of the first metal gate. A portion of the first metal gate is removed to form a first recess and followed by removing a portion of the protecting layer to form a second recess. Then, an etch stop layer is formed in the second recess.

Claims (11)

1. A semiconductor device comprising:

a substrate;

a transistor formed on the substrate, the transistor comprising a metal gate;

an etch stop layer formed on a top of the metal gate, a width of the etch stop layer being larger than a width of the metal gate; and

an interlayer dielectric (ILD) layer surrounding the transistor, a top of the etch stop layer and a top of the ILD layer being coplanar.

2. The semiconductor device according to claim 1 , further comprising a protecting layer covering sidewalls of the metal gate.

3. The semiconductor device according to claim 2 , wherein the protecting layer comprises at least a spacer.

4. The semiconductor device according to claim 3 , wherein the protecting layer further comprises a contact etch stop layer (CESL).

5. The semiconductor device according to claim 2 , wherein a bottom of the etch stop layer contacts a top of the protecting layer.

6. The semiconductor device according to claim 1 , wherein a thickness of the etch stop layer is between 250 Å and 400 Å.

7. The semiconductor device according to claim 1 , further comprising at least a contact plug formed in the ILD layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 19, 2013
From: WU, YI-CHING; HUANG, CHIH-SEN; HUNG, CHING-WEN
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 030639/0081 →
Continuity (1)
Related Publication 20140374805A1 · Dec 25, 2014