Back channel etch metal-oxide thin film transistor and process

1. A method of fabricating an organic light emitting diode (OLED) display, the method comprising:

forming a thin film transistor (TFT) substrate, the TFT having a gate electrode being formed from a first metal layer, a source electrode and a drain electrode being formed from a second metal layer, wherein the second metal layer is separated from the first metal layer by a gate insulator layer and a channel region is between the source electrode and the drain electrode;

depositing a first passivation layer over the second metal layer;

forming a third metal layer over the channel region and a storage capacitor region, the third metal layer being configured to connect to a first portion of the second metal layer that is configured to connect to the first metal layer in a first through-hole through the gate insulator and the first passivation layer;

depositing a second passivation layer over the third metal layer, the second passivation layer formed from silicon oxide (SiO2) or silicon nitride (SiNx);

forming an anode layer over the second passivation layer, the anode layer being directly connected to a second portion of the third metal layer that is connected to the second metal layer, the first portion of the third metal layer being separated from the second portion of the third metal layer by the second passivation layer.

2. The method of claim 1 , the step of forming an anode layer over the second passivation layer further comprising depositing an organic insulation layer over the second passivation layer, and forming an anode layer over the organic insulation layer, the anode being configured to connect to the second metal layer.

3. The method of claim 2 , wherein the organic insulator layer comprises a photoactive compound.

4. The method of claim 1 , the step of forming a thin film transistor (TFT) substrate further comprising:

forming the gate insulator over the first metal layer;

forming the channel layer over the gate insulator;

forming the source electrode and the drain electrode over the gate insulator and a first portion of the channel layer, the drain electrode being separated from the source electrode above a second portion of the channel layer.

5. The method of claim 3 , wherein the third metal layer is formed over the second portion of the channel layer for shielding light.

6. The method of claim 1 , wherein the third metal layer is configured to cover the storage capacitor region between a first TFT and a second TFT and is beyond an active region of a pixel.

7. The method of claim 1 , wherein the storage capacitor between the gate electrode and the anode layer has a storage capacitance as a sum of a first capacitance between the first metal layer and the second metal layer, a second capacitance between the second metal layer and the third metal layer, and a third capacitance between the third metal layer and the anode layer.

8. The method of claim 1 , wherein the first passivation layer comprises SiO2.

9. The method of claim 1 , wherein the anode comprises indium-tin oxide.

10. The method of claim 1 , wherein each of the first metal layer, second metal layer, and the third metal layer comprises copper.

11. The method of claim 1 , wherein the gate insulator comprises SiO2 and SiNx.

12. A method of fabricating an organic light emitting diode (OLED) display, the method comprising:

forming a thin film transistor (TFT) substrate, the TFT having a gate electrode being formed from a first metal layer, a source electrode and a drain electrode being formed from a second metal layer, wherein the second metal layer is separated from the first metal layer by a gate insulator layer, and a channel region is between the source electrode and the drain electrode;

depositing a passivation layer over the second metal layer;

forming a third metal layer that serves as an anode over the channel region, a storage capacitor region, and an OLED region, a first portion of the third metal layer being configured to connect to the second metal layer that is configured to connect to the first metal layer in a first through-hole of the gate insulator and the passivation layer, and a second portion of the third metal layer being configured to connect to the second metal layer in a second through-hole of the passivation layer;

forming a pixel defining layer over the third metal layer, the first portion of the third metal layer being separated from the second portion of the third metal layer by the pixel defining layer; and

forming a metal cathode layer over the pixel defining layer.

13. The method of claim 12 , the step of forming a third metal layer over the passivation layer further comprising depositing an organic insulation layer over the passivation layer, and forming a third metal layer over the organic insulation layer, a first portion of the third metal layer being configured to connect to the first metal layer and a second portion of the third metal layer being configured to connect to the second metal layer.

14. The method of claim 12 , the step of forming a thin film transistor (TFT) substrate further comprising:

forming the gate insulator over the first metal layer;

forming the channel layer over the gate insulator;

forming the source electrode and the drain electrode over the gate insulator and a first portion of the channel layer, the drain electrode being separated from the source electrode above a second portion of the channel layer.

15. The method of claim 14 , wherein the third metal layer is formed over the second portion of the channel layer for shielding light.

16. The method of claim 12 , wherein the third metal layer is configured to cover a storage capacitor region between a first transistor and a second transistor, an active region of a pixel, channel regions of the TFTs, and a data line such that the third metal layer is used for channel light shielding, reducing parasitic capacitance, and increasing storage capacitance of the storage capacitor.

17. The method of claim 12 , wherein the gate insulator layer and the passivation layer are positioned between the third metal layer and the first metal layer to reduce a parasitic capacitance between the third metal layer and the first metal layer.

18. The method of claim 12 , wherein the storage capacitor has a storage capacitance between the gate electrode and the third metal layer as a sum of a first capacitance between the first metal layer and the second metal layer and a second capacitance between the second metal layer and the third metal layer.

19. The method of claim 12 , wherein the OLED display is a bottom emission display such that light emits toward the third metal layer.