IP Library Granted Patent US 9,069,977
Granted Patent B2
US 9,069,977 · App. 13/337,731 · Granted Jun 30, 2015

Hybrid server with heterogeneous memory

Inventors: Yuk Lung Chan (Poughkeepsie, NY); Rajaram B. Krishnamurthy (Wappingers Falls, NY); Carl Joseph Parris (Rhinebeck, NY)
Assignee: International Business Machines Corporation
G06F21/602G06F12/0862G06F12/0868G06F17/30132G06F17/30194G06F2212/264H04L29/08729G06F15/177
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Quick Facts
Patent No.
US 9,069,977
App. No.
13/337,731
Granted
Jun 30, 2015
Kind
B2
Abstract

A method, hybrid server system, and computer program product, for managing access to data stored on the hybrid server system. A memory system residing at a server is partitioned into a first set of memory managed by the server and a second set of memory managed by a set of accelerator systems. The set of accelerator systems are communicatively coupled to the server. The memory system comprises heterogeneous memory types. A data set stored within at least one of the first set of memory and the second set of memory that is associated with at least one accelerator system in the set of accelerator systems is identified. The data set is transformed from a first format to a second format, wherein the second format is a format required by the at least one accelerator system.

Claims (45)

1. A method, on a hybrid server system, for managing access to data stored thereon, the method comprising:

partitioning a memory system residing at a server into a first set of memory managed by the server and a second set of memory managed by a set of accelerator systems, the second set of memory being directly writeable to by the set of accelerator systems, wherein the set of accelerator systems are separate from and communicatively coupled to the server, and wherein the memory system comprises heterogeneous memory types;

identifying a data set stored within at least one of the first set of memory and the second set of memory that is associated with at least one accelerator system in the set of accelerator systems; and

transforming the data set from a first format to a second format, wherein the second format is a format required by the at least one accelerator system.

2. The method of claim 1 , wherein the transforming is based on at least one of an operation associated with the data set and a type of processing core residing on the at least one accelerator system.

3. The method of claim 1 , wherein partitioning the memory system comprises:

releasing the second set of memory to the set of accelerator systems.

4. The method of claim 1 , further comprising:

determining that at least one accelerator system in the set of accelerator systems has completed processing data in a given portion of memory residing on the at least one accelerator system; and

accessing, in response to the determining, the given portion of memory.

5. The method of claim 1 , further comprising:

determining that at least one data block within a fast memory of the memory system has been replaced;

moving the replaced data block from the fast memory to a slow memory of the memory system; and

moving the replaced data block from the slow memory to a disk storage.

6. The method of claim 1 , further comprising:

communicating, by a first accelerator system in the set of accelerator systems, at least one data set residing within a flash memory module of the memory system to a second accelerator system in the set of accelerator systems over an input-output bus of the server, wherein the at least one flash memory module is communicatively coupled to the input-output bus of the server, and wherein the first and second accelerator systems have direct access to the at least one flash memory module.

7. The method of claim 6 , wherein the at least one flash memory module comprises a network link configured to at least one of send and receive messages from at least the set of accelerators.

8. The method of claim 1 , wherein each accelerator in the set of accelerators is assigned a private memory module within the memory system, and a public memory area within the memory system, wherein the public memory area is accessible by two or more accelerators in the set of accelerators.

9. A hybrid server system in an out-of-core processing environment comprising:

a server comprising

a memory system partitioned into a first set of memory managed by the server, and a second set of memory managed by a set of accelerator systems, wherein the memory system comprises heterogeneous memory types, and

a data access manager communicatively coupled to the memory system; and

a set of accelerator systems communicatively coupled to the server, wherein each accelerator system in the set of accelerator systems comprises at least one processing core, wherein each accelerator in the set of accelerators is assigned a private memory module within the memory system, and a public memory area within the memory system, wherein the public memory area is accessible by two or more accelerators in the set of accelerators, and

wherein the data access manager is configured to

identify a data set stored within at least one of the first set of memory and the second set of memory that is associated with at least one accelerator system in the set of accelerator systems; and

transform the data set from a first format to a second format, wherein the second format is a format required by the at least one accelerator system.

10. The hybrid server system of claim 9 , wherein the transforming is based on at least one of an operation associated with the data set and a type of the at least one processing core of the at least one accelerator system.

11. The hybrid server system of claim 9 , wherein partitioning the memory system comprises:

releasing the second set of memory to the set of accelerator systems.

12. The hybrid server system of claim 9 , wherein at least one accelerator system in the set of accelerator systems comprises at least one gated memory, wherein the at least one accelerator system selectively allows the server to access the at least one gate memory.

13. The hybrid server system of claim 9 , wherein the memory system comprises at least one flash memory module, and wherein the at least one flash memory module is communicatively coupled to an input-output bus of the server, wherein a first accelerator system in the set of accelerator systems communicates at least one data set residing within the flash memory to a second accelerator system in the set of accelerator systems over the input-output bus of the server, and wherein the first and second accelerator systems have direct access to the at least one flash memory module.

14. The hybrid server system of claim 13 , wherein the at least one flash memory module comprises a network link configured to at least one of send and receive messages from at least the set of accelerators.

15. A computer program product for managing data access in an out-of-core processing environment, the computer program product comprising:

a non-transitory storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:

partitioning a memory system residing at a server into a first set of memory managed by the server and a second set of memory managed by a set of accelerator systems, the second set of memory being directly writeable to by the set of accelerator systems, wherein the set of accelerator systems are separate from communicatively coupled to the server, and wherein the memory system comprises heterogeneous memory types;

identifying a data set stored within at least one of the first set of memory and the second set of memory that is associated with at least one accelerator system in the set of accelerator systems; and

transforming the data set from a first format to a second format, wherein the second format is a format required by the at least one accelerator system.

16. The computer program product of claim 15 , wherein the transforming is based on at least one of an operation associated with the data set and a type of processing core residing on the at least one accelerator system.

17. The computer program product of claim 15 , wherein the method further comprises:

determining that at least one data block within a fast memory of the memory system has been replaced;

moving the replaced data block from the fast memory to a slow memory of the memory system; and

moving the replaced data block from the slow memory to a disk storage.

18. The computer program product of claim 15 , wherein the method further comprises:

communicating, by a first accelerator system in the set of accelerator systems, at least one data set residing within a flash memory module of the memory system to a second accelerator system in the set of accelerator systems over an input-output bus of the server, wherein the at least one flash memory module is communicatively coupled to the input-output bus of the server, and wherein the first and second accelerator systems have direct access to the at least one flash memory module.

19. The computer program product of claim 15 , wherein each accelerator in the set of accelerators is assigned a private memory module within the memory system, and a public memory area within the memory system, wherein the public memory area is accessible by two or more accelerators in the set of accelerators.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 6, 2025
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: BLUE HERON DEVELOPMENT LLC
Reel/Frame 070130/0844 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 20, 2024
From: CHAN, YUK LUNG; KRISHNAMURTHY, RAJARAM B.; PARRIS, CARL JOSEPH
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 069647/0657 →
Continuity (3)
Continuation 12822760 · Jun 24, 2010
Continuation 12822790 · Jun 24, 2010
Related Publication 20120117312A1 · May 10, 2012