Semiconductor memory devices and semiconductor packages

1. A semiconductor memory device comprising:

a plurality of semiconductor dies that are stacked, each semiconductor die including a plurality of memory cell arrays; and

a plurality of input-output bump pad parts respectively located at a central region of each semiconductor die, the input-output bump pad parts providing a plurality of channels each dedicated to only a respective one of the memory cell arrays and by which each of the memory cell arrays can be connected independently of each other to one or more external devices,

wherein each of the input-output bump pad parts includes a plurality of channel bump pad parts associated with the memory cell arrays, respectively,

each of the channel bump pad parts includes a plurality of bump pads that are arranged in a matrix of rows and columns, and

the bump pads of each of the channel bump parts include power bump pads dedicated to receive power supply voltages.

2. The semiconductor memory device of claim 1 , wherein each of the channel bump pad parts comprises an address-command pad block including address-command bump pads, and a plurality of data pad blocks each including data bump pads.

3. The semiconductor memory device of claim 2 , wherein the address-command pad block is disposed between the data pad blocks or at one side of the plurality of the data pad blocks.

4. The semiconductor memory device of claim 2 , wherein each of the data pad blocks also includes at least one row of respective ones of the power bump pads.

5. The semiconductor memory device of claim 2 , wherein each of the data pad blocks also includes at least one column of respective ones of the power bump pads.

6. The semiconductor memory device of claim 2 , wherein each of the data pad blocks includes respective ones of the power bump pads, the power bump pads of each of the data pad blocks are disposed in a central region of the data pad block, and the data bump pads of each of the data pad blocks surround the power bump pads of the data pad block.

7. The semiconductor memory device of claim 2 ,

wherein each semiconductor die includes a substrate, and an output driver, a decoupling capacitor and an input buffer disposed in the substrate under each data bump pad.

8. The semiconductor memory device of claim 1 , wherein each semiconductor die includes a plurality of input-output control circuits, each of the input-output control circuits being disposed between a corresponding one of the memory cell arrays and a corresponding one of the channel bump pad parts.

9. The semiconductor memory device of claim 8 , wherein a row-directional length of each input-output control circuit is identical to or smaller than a row-directional length of each channel bump pad part.

10. The semiconductor memory device of claim 8 , wherein each of the data pad blocks includes N data bump pads, where N is a positive integer, and

wherein N output drivers and N input buffers are disposed in the corresponding input-output control circuit and in the semiconductor die under the corresponding channel bump pad part.

11. The semiconductor memory device of claim 1 , wherein the bump pads of each of the channel bump pad parts also include a plurality of address-command bump pads, and

each semiconductor die further includes a substrate, and a decoupling capacitor disposed in the substrate under each address-command bump and under each power bump pad.

12. The semiconductor memory device of claim 11 , wherein each semiconductor die further includes at least one clamp diode and one electrostatic discharge protection circuit disposed in the substrate under each address-command bump pad.

13. The semiconductor memory device of claim 11 , wherein each semiconductor die further includes an electrostatic discharge protection circuit disposed in the substrate under each power bump pad.

14. The semiconductor memory device of claim 1 , further comprising:

a plurality of support bump pad parts, each support bump pad part being disposed adjacent to four corners of each semiconductor die or disposed adjacent to two or more sides of each semiconductor die.

15. The semiconductor memory device of claim 14 , wherein each support bump pad part includes power bump pads receiving power supply voltages.

16. The semiconductor memory device of claim 1 , wherein each semiconductor die further includes through-silicon-vias for electrically connecting the input-output bump pad parts.

17. A semiconductor memory device comprising:

a plurality of semiconductor dies that are stacked, each semiconductor die including a plurality of memory cell arrays;

a plurality of input-output bump pad parts respectively located at a central region of each semiconductor die, the input-output bump pad parts providing a plurality of channels each dedicated to only a respective one of the memory cell arrays and by which each of the memory cell arrays can be connected independently of each other to one or more external devices; and

a plurality of test pad parts respectively located at each semiconductor die for testing operations of the semiconductor memory device.

18. The semiconductor memory device of claim 17 , wherein the test pad part is disposed in a column direction along a vertical center line of the semiconductor die, or disposed in the column direction adjacent to left and right sides of the semiconductor die.

19. The semiconductor memory device of claim 17 , wherein the test pad part is disposed in a row direction along a horizontal center line of the semiconductor die, or disposed in the row direction adjacent to upper and bottom sides of the semiconductor die.

20. A semiconductor package comprising:

a base substrate;

a controller chip disposed on the base substrate; and

at least one semiconductor memory device disposed on the controller chip, the semiconductor memory device comprising:

a semiconductor die including,

a plurality of memory cell arrays; and

an input-output bump pad part located at a central region of the semiconductor die, the input-output bump pad part providing a plurality of channels each dedicated to only a respective one of the memory cell arrays and by which each of the memory cell arrays can be connected independently of each other to the controller chip,

wherein each of the input-output bump pad parts includes a plurality of channel bump pad parts associated with the memory cell arrays, respectively,

each of the channel bump pad parts includes a plurality of bump pads that are arranged in a matrix of rows and columns, and

the bump pads of each of the channel bump parts include power bump pads dedicated to receive power supply voltages.