Methods for forming arrays of small, closely spaced features
Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed patterns of crossing elongate features with pillars at the intersections. Spacers are simultaneously applied to sidewalls of both sets of crossing lines to produce a pitch-doubled grid pattern. The pillars facilitate rows of spacers bridging columns of spacers.
1. A method of forming an integrated circuit, comprising:
forming a temporary layer over a substrate;
partially etching the temporary layer with a first pattern such that less than an entire thickness of the temporary layer is penetrated upon completing partially etching the temporary layer with the first pattern;
subsequently partially etching the temporary layer with a second pattern;
removing remaining portions of the temporary layer;
patterning the substrate with a mask derived from the partially etched temporary layer,
wherein some regions of the temporary layer are substantially unetched during partially etching the temporary layer with the first pattern and during subsequently partially etching the temporary layer with the second pattern,
wherein the regions of the temporary layer that are unetched form pillars at the intersections of an underlying grid, and
further comprising forming spacers at sidewalls of the pillars and the grid.
2. The method of claim 1 , wherein the first pattern comprises a plurality of lines extending substantially along a first axis.
3. The method of claim 2 , wherein the second pattern comprises a plurality of lines extending substantially along a second axis crossing the first axis.
4. The method of claim 1 , wherein forming spacers comprises:
blanket depositing a layer of spacer material over the pillars and the grid; and
subjecting the layer of spacer material to a directional etch to define the spacers and expose portions of the temporary layer.
5. The method of claim 1 , further comprising removing the exposed portions of the temporary layer to leave a hard mask grid formed by the spacers.
6. The method of claim 5 , wherein the spacers extend continuously between the pillars and the grid.
7. The method of claim 5 , wherein patterning the substrate comprises transferring a pattern defined by the spacers to the substrate.
8. The method of claim 7 , wherein transferring the pattern comprises etching openings in the substrate.
9. The method of claim 8 , further comprising depositing conductive material into the openings.
10. The method of claim 9 , wherein depositing the conductive material forms parts of memory cells.
11. The method of claim 1 , wherein the first pattern and the second pattern at least partially overlap.
12. The method of claim 1 , wherein some regions of the temporary layer are etched during both partially etching the temporary layer with the first pattern and subsequently partially etching the temporary layer with the second pattern.
13. The method of claim 12 , wherein some regions of the temporary layer are etched only once during partially etching the temporary layer with the first pattern and subsequently partially etching the temporary layer with the second pattern.
14. The method of claim 1 , further comprising depositing a filler material in voids of the first pattern before subsequently partially etching.
15. The method of claim 14 , wherein depositing the filler material comprises performing a spin on deposition.
16. The method of claim 1 , wherein the temporary layer comprises amorphous carbon.
17. The method of claim 1 , wherein the substrate is a semiconductor wafer.