IP Library Granted Patent US 9,087,202
Granted Patent B2
US 9,087,202 · App. 13/891,255 · Granted Jul 21, 2015

Entry/exit architecture for protected device modules

Inventors: Xiaozhu Kang (Fremont, CA); Alpa T. Narendra Trivedi (Hillsboro, OR); Siddhartha Chhabra (Hillsboro, OR); Prashant Dewan (Hillsboro, OR); Uday R. Savagaonkar (Portland, OR); David M. Durham (Beaverton, OR)
Assignee: Intel Corporation
G06F21/60G06F21/50G06F21/78G06F12/14
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Quick Facts
Patent No.
US 9,087,202
App. No.
13/891,255
Granted
Jul 21, 2015
Kind
B2
Abstract

The entry/exit architecture may be a critical component of a protection framework using a secure enclaves-like trust framework for coprocessors. The entry/exit architecture describes steps that may be used to switch securely into a trusted execution environment (entry architecture) and out of the trusted execution environment (exit architecture), at the same time preventing any secure information from leaking to an untrusted environment.

Claims (38)

1. A method comprising:

executing a command on a graphics processor that takes a pointer to a device thread control structure belonging to an enclave-device-module;

entering the enclave-device-module on the graphics processor; and

fetching commands from a buffer inside the enclave-device-module on the graphics processor.

2. The method of claim 1 including marking the structure as busy when the enclave-device-module is entered.

3. The method of claim 1 including making a synchronous entry to an enclave-device-module.

4. The method of claim 1 including making an asynchronous entry to an enclave-device-module.

5. The method of claim 1 including making a synchronous entry on the first entry to an enclave-device-module and using an asynchronous entry thereafter.

6. The method of claim 5 including using a flag to indicate whether to enter synchronously or asynchronously.

7. The method of claim 1 including exiting from an enclave-device-module using a command executed inside the buffer.

8. The method of claim 1 including using unprivileged entry commands.

9. The method of claim 1 including using a memory write to a memory management input output device register in order to enter an enclave-device-module.

10. The method of claim 1 including executing a command in a graphics processor to enter an enclave-device-module.

11. One or more non-transitory computer readable media storing instructions to perform a sequence comprising:

executing a command that points to a device thread control structure of an enclave-device-module;

entering the enclave-device-module; and

fetching commands from inside the enclave-device-module.

12. The media of claim 11 including marking the structure as busy when the enclave-device-module is entered.

13. The media of claim 11 including making a synchronous entry to an enclave-device-module.

14. The media of claim 11 including making an asynchronous entry to an enclave-device-module.

15. The media of claim 11 including making a synchronous entry on the first entry to an enclave-device-module and using an asynchronous entry thereafter.

16. The media of claim 15 including using a flag to indicate whether to enter synchronously or asynchronously.

17. The media of claim 11 including exiting from an enclave-device-module using a command executed inside a buffer.

18. The media of claim 11 including using unprivileged entry commands.

19. The media of claim 11 including using a memory write to a memory management input output device register in order to enter an enclave-device-module.

20. The media of claim 11 including executing a command in a graphics processor to enter an enclave-device-module.

21. An apparatus comprising:

a memory; and

a processor, coupled to said memory, to execute a command that takes a pointer to a device thread control structure belonging to an enclave-device-module, enter the enclave-device-module, and fetch commands from the memory inside the enclave-device-module.

22. The apparatus of claim 21 , said processor to mark the structure as busy when the enclave-device-module is entered.

23. The apparatus of claim 21 , said processor to make a synchronous entry to an enclave-device-module.

24. The apparatus of claim 21 , said processor to make an asynchronous entry to an enclave-device-module.

25. The apparatus of claim 21 , said processor to make a synchronous entry on the first entry to an enclave-device-module and using an asynchronous entry thereafter.

26. The apparatus of claim 25 , said processor to use a flag to indicate whether to enter synchronously or asynchronously.

27. The apparatus of claim 21 , said processor to exit from an enclave-device-module using a command executed inside the memory.

28. The apparatus of claim 21 including an operating system.

29. The apparatus of claim 21 including firmware and a module to update said firmware.

30. The apparatus of claim 21 , said processor to use a memory write to a memory management input output device register in order to enter an enclave-device-module.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 25, 2014
From: KANG, XIAOZHU; TRIVEDI, ALPA T. NARENDRA; CHHABRA, SIDDHARTHA; DEWAN, PRASHANT; SAVAGAONKAR, UDAY R.; DURHAM, DAVID M.
To: INTEL CORPORATION
Reel/Frame 034261/0200 →
Continuity (1)
Related Publication 20140337983A1 · Nov 13, 2014