IP Library Granted Patent US 9,087,981
Granted Patent B2
US 9,087,981 · App. 13/763,293 · Granted Jul 21, 2015

Methods of forming a magnetic tunnel junction device

Inventors: Chern-Yow Hsu (Chu-Bei, TW); Shih-Chang Liu (Alian Township, TW); Chia-Shiung Tsai (Hsin-Chu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L43/12
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Quick Facts
Patent No.
US 9,087,981
App. No.
13/763,293
Granted
Jul 21, 2015
Kind
B2
Abstract

Embodiments of the present disclosure are a method of forming a magnetic tunnel junction (MTJ) device and methods of forming a magnetic random access memory (MRAM) device. An embodiment is a method of forming a magnetic tunnel junction (MTJ) device, the method comprising forming an MTJ layer over a bottom electrode, forming a top electrode layer over the MTJ layer, and selectively etching the top electrode layer to form a top electrode over the MTJ layer. The method further comprises patterning an upper portion of the MTJ layer with an ion beam etch (IBE) process.

Claims (50)

1. A method of forming a magnetic tunnel junction (MTJ) device, the method comprising:

forming an MTJ layer over a bottom electrode, the forming the MTJ layer further comprises:

forming an anti-ferromagnetic (AFM) layer over the bottom electrode;

forming a pinned layer over the AFM layer;

forming a barrier layer over the pinned layer; and

forming a free layer over the barrier layer;

forming a top electrode layer over the MTJ layer;

selectively etching the top electrode layer to form a top electrode over the MTJ layer;

patterning the free layer with an ion beam etch (IBE) process; and

forming spacers on sides of the top electrode and the free layer, sidewalls of the spacers directly adjoining the top electrode and the free layer, bottom surfaces of the spacers directly adjoining top surfaces of the barrier layer.

2. The method of claim 1 , wherein the IBE process stops on the barrier layer.

3. The method of claim 1 further comprising:

after the forming the spacers, patterning the barrier layer, the pinned layer, and the AFM layer.

4. The method of claim 1 , wherein the forming spacers on sides of the top electrode and the free layer further comprises:

forming a first dielectric layer over the top electrode and the MTJ layer; and

patterning the first dielectric layer to remove the horizontal surfaces of the first dielectric layer.

5. The method of claim 1 further comprising encapsulating the top electrode, the spacers, the MTJ layer, and the bottom electrode with a second dielectric layer.

6. The method of claim 3 , wherein the patterning the barrier layer, the pinned layer, and the AFM layer further comprises performing a second IBE process.

7. A method of forming a magnetic random access memory (MRAM) device, the method comprising:

forming a magnetic tunnel junction (MTJ) layer over a bottom electrode, the MTJ layer including a free layer;

forming a top electrode layer over the MTJ layer;

etching the top electrode layer to form a top electrode over the MTJ layer; and

patterning the free layer of the MTJ layer with a multi-step ion beam etching (IBE) process, the patterning the free layer of the MTJ layer with a multi-step IBE process further comprises:

performing a first IBE process on the free layer at a first angle of incidence;

performing a second IBE process on the free layer at a second angle of incidence, the second angle of incidence being different from the first angle of incidence, the first IBE process forming a film on sidewalls of the top electrode, and the second IBE process removing the film from the sidewalls of the top electrode; and

performing a third IBE process on the free layer at a third angle of incidence, the third angle of incidence being different from the second angle of incidence.

8. The method of claim 7 , wherein the second angle of incidence is larger than the first angle of incidence and the third angle of incidence as measured from a line orthogonal to a top surface of the bottom electrode.

9. The method of claim 7 , wherein the first angle of incidence is between about 0 and about 25 as measured from a line orthogonal to a top surface of the bottom electrode, and wherein the second angle of incidence is between about 55 and about 89 as measured from the line orthogonal to the top surface of the bottom electrode.

10. The method of claim 7 , wherein the film on the sidewalls of the top electrode comprises a re-deposited etching by-product from the first IBE process.

11. The method of claim 7 , wherein the multi-step IBE process comprises an etchant gas from a group consisting essentially of CHF 2 , CHF 3 , or CHF 4 , Ar, O, N, or a combination thereof.

12. The method of claim 7 further comprising forming a dielectric layer over the bottom electrode, the MTJ layer, and the top electrode.

13. A method of forming a magnetic random access memory (MRAM) device, the method comprising:

forming an anti-ferromagnetic (AFM) layer;

forming a pinned layer over the AFM layer;

forming a barrier layer over the pinned layer;

forming a free layer over the barrier layer;

performing an ion beam etching (IBE) process to pattern the free layer, wherein the IBE process stops on the barrier layer;

forming spacers on sidewalls of the free layer; and

encapsulating the AFM layer, the pinned layer, the barrier layer, and the spacers with a dielectric layer, the dielectric layer directly adjoining the spacers, the barrier layer, and the pinned layer.

14. The method of claim 13 , wherein the IBE process is a multi-step IBE process, the multi-step process comprising ions with at least two angle of incidences.

15. The method of claim 13 further comprising patterning the barrier layer, the pinned layer, and the AFM layer, thereby forming a magnetic tunnel junction (MTJ).

16. The method of claim 15 further comprising:

forming a bottom electrode under the MTJ; and

forming a top electrode over the MTJ, the dielectric layer encapsulating the top electrode, the MTJ, and the bottom electrode.

17. The method of claim 13 , wherein sidewalls of the spacers directly adjoin the free layer and bottom surfaces of the spacers directly adjoin top surfaces of the barrier layer.

18. The method of claim 13 further comprising after the forming the spacers, patterning the barrier layer, the pinned layer, and the AFM layer.

19. The method of claim 1 , wherein the patterning the free layer with an IBE process further comprises:

performing a first IBE process on the free layer at a first angle of incidence; and

performing a second IBE process on the free layer at a second angle of incidence, the second angle of incidence being different from the first angle of incidence, the first IBE process forming a film on sidewalls of the top electrode, and the second IBE process removing the film from the sidewalls of the top electrode.

20. The method of claim 5 , wherein the second dielectric layer directly adjoins the spacers, the barrier layer, and the pinned layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 1, 2013
From: HSU, CHERN-YOW; LIU, SHIH-CHANG; TSAI, CHIA-SHIUNG
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 029901/0905 →
Continuity (1)
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