Storage of codeword portions
Embodiments of the present disclosure describe device, methods, computer-readable media and system configurations for dividing error correcting code (“ECC”) codewords into portions and storing the portions among multiple die of non-volatile memory (“NVM”). For example, a device may include memory including a first die and a second die, and a memory controller configured to store a first portion of a codeword for use with an error correcting code in a first segment of the first die and to store a second portion of the codeword in a first segment of the second die. In various embodiments, the first segment of the second die may be offset from the first segment of the first die. Other embodiments may be described and/or claimed.
1. A device comprising:
non-volatile memory including a first die and a second die; and
a memory controller configured to store a first portion of a codeword for use with an error correcting code in a first segment of the first die and to store a second portion of the codeword in a first segment of the second die, wherein the first segment of the second die is offset from the first segment of the first die.
2. The device of claim 1 , wherein the non-volatile memory is NAND flash memory.
3. The device of claim 1 , wherein the codeword is a first codeword, and the memory controller is further configured to store a first portion of a second codeword for use with the error correcting code in a second segment of the second die, and to store a second portion of the second codeword in a second segment of the first die.
4. The device of claim 3 , wherein the second segment of the second die is offset from the second segment of the first die.
5. The device of claim 4 , wherein the first segment of the first die is vertically aligned with the second segment of the second die and the second segment of the first die is vertically aligned with the first segment of the second die.
6. The device of claim 1 , wherein XOR results of contents of the first and second die are distributed among multiple die.
7. The device of claim 6 , the memory controller is further configured to:
determine that the second die has failed;
reconstruct the second codeword portion based at least in part on an XOR result of the XOR results; and
decode the codeword with the first portion of the codeword and the reconstructed second portion of the first codeword.
8. The device of claim 1 , wherein the first segment of the second die is logically offset, by the memory controller, from the first segment of the first die.
9. A method, comprising:
storing a first portion of a codeword for use with an error correcting code in a first segment of a first die of non-volatile memory; and
storing a second portion of the codeword in a first segment of a second die of the non-volatile memory that is physically or logically offset from the first segment of the first die.
10. The method of claim 9 , wherein the codeword is a first codeword, the method further comprising:
storing a first portion of a second codeword for use with the error correcting code in a second segment of the second die; and
storing a second portion of the second codeword in a second segment of the first die that is physically or logically offset from the second segment of the second die.
11. The method of claim 9 , further comprising distributing XOR results of the first and second die among multiple die.
12. The method of claim 11 , further comprising:
determining that the second die has failed;
reconstructing the second codeword portion based at least in part on an XOR result of the XOR results; and
decoding the codeword with the first portion of the codeword and the reconstructed second portion of the first codeword.
13. The method of claim 10 , wherein the first segment of the first die is vertically aligned with the second segment of the second die.
14. The method of claim 13 , wherein the second segment of the first die is vertically aligned with the first segment of the second die.
15. The method of claim 9 , wherein the non-volatile memory is NAND flash memory.
16. The method of claim 9 , further comprising selectively implementing an error correcting code based on raw bit error rate variability among a population of devices.
17. A system comprising:
one or more processors;
non-volatile memory operably coupled to the one or more processors;
a liquid crystal display screen operably coupled to the one or more processors; and
a memory controller to be operated by the one or more processors and configured to store a first portion of a codeword for use with an error correcting code in a first segment of a first die of the non-volatile memory and to store a second portion of the codeword in a first segment of a second die of the non-volatile memory, wherein the first segment of the second die is logically or physically offset from the first segment of the first die.
18. The system of claim 17 , wherein the non-volatile memory is NAND flash memory.
19. The system of claim 17 , wherein the error correcting code is selected from a plurality of potential error correcting codes to account for raw bit error rate variability among a population of systems of which the system is a member.
20. The system of claim 17 , wherein the codeword is a first codeword, and the memory controller is further configured to store a first portion of a second codeword for use with the error correcting code in a second segment of the second die, and to store a second portion of the second codeword in a second segment of the first die.
21. The system of claim 17 , wherein XOR results of the contents of the first and second die are distributed among multiple die.
22. The system of claim 21 , the memory controller is further configured to:
determine that the second die has failed;
reconstruct the second codeword portion based at least in part on an XOR result of the XOR results; and
decode the codeword with the first portion of the codeword and the reconstructed second portion of the first codeword.