Method of detecting fault attack
In a method of detecting a fault attack in a secure memory device, payload data is initialized by determining whether the payload data is consistent. The payload data is stored in a plurality of ephemeral registers included in the secure memory device. A count value included in the payload data is increased by detecting whether a fault is injected in the secure memory device from outside, during a processing operation of secure data, stored in the secure memory device. It is determined whether the fault injected in the secure memory device from the outside is caused by the fault attack based on the count value and a threshold value.
1. A method of detecting a fault attack in a secure memory device, the method comprising:
initializing payload data by determining whether the payload data is consistent, the payload data being stored in a plurality of ephemeral registers included in the secure memory device;
increasing a count value included in the payload data by detecting whether a fault is injected in the secure memory device from outside, during a processing operation of secure data, stored in the secure memory device; and
determining whether the fault injected in the secure memory device from the outside is caused by the fault attack based on the count value and a threshold value.
2. The method of claim 1 , wherein the payload data further includes an error detection code (EDC) value corresponding to the count value, the count value includes a plurality of count bits, and the EDC value includes a plurality of EDC bits, and
wherein the initializing the payload data comprises:
determining whether a first count bit of the plurality of count bits matches with first EDC bits of the plurality of EDC bits, the first EDC bits corresponding to the first count bit.
3. The method of claim 2 , wherein the initializing the payload data further comprises:
maintaining the payload data at a previous logic state if the first count bit matches with the first EDC bits; and
initializing the payload data if the first count bit does not match with the first EDC bits.
4. The method of claim 3 , wherein the payload data is maintained at the previous logic state if the secure memory device is powered on within a data retention time of the ephemeral registers, and the payload data is initialized if the secure memory device is powered on after the data retention time of the ephemeral registers has elapsed.
5. The method of claim 1 , wherein the increasing the count value comprises:
maintaining the count value to a previous value if the fault is not injected in the secure memory device; and
increasing the count value if the fault is injected in the secure memory device.
6. The method of claim 1 , wherein the determining whether the fault is caused by the fault attack comprises:
determining that the fault is caused by a single event upset (SEU) if the count value is less than or equal to the threshold value; and
determining that the fault is caused by the fault attack if the count value is greater than the threshold value.
7. The method of claim 1 , further comprising:
initializing the payload data if the fault is not injected in the secure memory device from the outside within a reference time period.
8. The method of claim 1 , further comprising:
terminating the processing operation of the secure memory device.
9. The method of claim 8 , wherein the terminating the processing operation of the secure memory device comprises:
resetting the processing operation of the secure memory device if the fault is determined as being caused by a SEU; and
terminating the processing operation of the secure memory device if the fault is determined as being caused by the fault attack.
10. The method of claim 9 , wherein the secure memory device comprises:
a security detector which is configured to generate a detection signal by detecting whether the fault is injected in the secure memory device, and configured to generate an alarm signal indicating whether the fault is caused by the fault attack; and
a processor which is configured to control the operation of the secure memory device, configured to increase the count value based on the detection signal, and configured to terminate the processing operation of the secure memory device based on the alarm signal.
11. The method of claim 9 , wherein the secure memory device comprises:
a security detector which is configured to generate a detection signal by detecting whether the fault is injected in the secure memory device;
a register controller which is configured to increase the count value based on the detection signal, and configured to generate an alarm signal indicating whether the fault is caused by the fault attack; and
a processor which is configured to control the operation of the secure memory device, and configured to terminate the processing operation of the secure memory device based on the alarm signal.
12. The method of claim 1 , wherein each ephemeral register of the ephemeral registers comprise:
a storage block which is configured to store at least one of a plurality of bits included in the payload data;
a first diode which is connected between the storage block and a terminal of a first voltage;
a second diode which is connected between the storage block and a terminal of a second voltage; and
a power supply block which is connected in parallel with the storage block, and supplies power to the storage block.
13. The method of claim 12 , wherein the storage block comprises a flip-flop or a latch, and the power supply block comprises a capacitor.
14. The method of claim 12 , wherein a data retention time of each ephemeral register is determined based on a structure of the storage block and a charge storage characteristic of the power supply block.
15. A method of detecting a fault attack in a secure memory device, the method comprising:
generating a first determination result, by initializing first payload data as a result of determining whether the payload data is consistent, increasing a first count value included in the first payload data as a result of detecting whether a fault is injected in the secure memory device from outside during a processing operation of secure data, stored in the secure memory device, and determining whether the fault is caused by the fault attack based on the first count value and a first threshold value, the first payload data being stored in a plurality of first ephemeral registers included in the secure memory device;
generating a second determination result, by initializing second payload data as a result of determining whether the second payload data is consistent, increasing a second count value included in the second payload data as a result of detecting whether the fault is injected in the secure memory device from the outside during the processing operation of the secure data, stored in the secure memory device, and determining whether the fault is caused by the fault attack based on the second count value and a second threshold value, different from the first threshold value, the second payload data being stored in a plurality of second ephemeral registers included in the secure memory device, and a data retention time of the second ephemeral registers being different from a data retention time of the first ephemeral registers; and
terminating the processing operation of the secure memory device based on the first determination result and the second determination result.
16. A method of detecting a fault attack in a secure memory device, the method comprising:
determining whether a first count bit, of a plurality of count bits, matches with a plurality of first error detection code (EDC) bits corresponding with the first count bit;
initializing payload data if the first count bit does not match the first EDC bits;
detecting whether a fault is injected in the secure memory device from outside during a processing operation of the secure memory device;
increasing a count value included in the payload data when the fault is injected in the secure memory device; and
determining whether the fault injected in the secure memory device from the outside in a single event upset (SEU) or the fault attack.
17. The method of claim 16 , wherein the determining whether the fault injected in the secure memory device from the outside is the SEU occurs when the count value is less than or equal to a threshold value.
18. The method of claim 16 , wherein the determining whether the fault injected in the secure memory device from the outside is the fault attack occurs when the count value is greater than a threshold value.
19. The method of claim 17 , wherein when the fault injected is determined to be the SEU, resetting the processing operation of the secure memory device.
20. The method of claim 18 , wherein when the fault injected is determined to be the fault attack, terminating the processing operation of the secure memory device.