Diode, ESD protection circuit and method of manufacturing the same

1. A diode, the diode comprising:

an N-type well region disposed in an N-type epitaxial layer;

a P-type drift region disposed in the N-type epitaxial layer, wherein the P-type drift region is spaced apart from the N-type well region;

a cathode electrode including a first electrode and an N-type doping region, wherein the N-type doping region is electrically coupled to the first electrode, the N-type well region includes the N-type doping region only and does not include a P-type doping region, and the first electrode is disposed on the N-type epitaxial layer;

an anode electrode including a P-type doping region, wherein the P-type doping region is disposed in the P-type drift region; and

an isolation structure disposed in the P-type drift region, wherein the isolation structure is disposed between the N-type well region and the P-type doping region,

wherein the first electrode of the cathode overlaps part of the isolation structure,

wherein the first electrode corresponds to a gate of a P-type LDMOS transistor,

wherein the N-type well region, the P-type drift region, the P-type doping region, and the isolation structure of the diode corresponds to an N-type well region, a P-type drift region, a drain region, and an isolation structure of a P-type LDMOS transistor, respectively.

2. The diode of claim 1 , further comprising:

an interlayer dielectric disposed on the first electrode and the N-type epitaxial layer,

a first vertical contact penetrating the interlayer dielectric layer and coupled to the N-type doping region;

a second vertical contact spaced apart from the first vertical contact and penetrating the interlayer dielectric layer and coupled to the N-type doping region;

a third vertical contact penetrating the interlayer dielectric layer and coupled to the first electrode;

a fourth vertical contact penetrating the interlayer dielectric layer and coupled to the P-type doping region; and

a second electrode disposed on the interlayer dielectric layer and coupled to the first electrode, the first vertical contact, and the second vertical contact.

3. The diode of claim 2 ,

wherein the first electrode of the cathode electrode is doped with an N-type dopant.

4. The diode of claim 1 ,

wherein a P-type doping region corresponding to a source region of the P-type LDMOS transistor is not disposed in the N-type well region, and

wherein the N-type doping region of the cathode is extended to a region corresponding to the source region of the P-type LDMOS transistor.

5. The diode of claim 1 , wherein the N-type epitaxial layer is disposed on a semiconductor substrate.

6. The diode of claim 5 , further comprising:

a P-type well region disposed in the N-type epitaxial layer,

wherein the P-type drift region is disposed in the P-type well region.

7. The diode of claim 5 , further comprising:

an N-type buried layer disposed in an upper portion of the semiconductor substrate,

wherein the N-type epitaxial layer is disposed on the N-type buried layer.

8. An electrostatic discharge (ESD) protection circuit comprising:

an N-type lateral diffused metal oxide semiconductor (LDMOS) transistor including a gate, a source electrode, and a drain electrode, wherein the source electrode is coupled to a first pad to which a first voltage is applied, and wherein the drain electrode is coupled to a second pad to which a second voltage higher than the first voltage is applied;

a diode comprising:

an N-type well region disposed in an N-type epitaxial layer;

a P-type drift region disposed in the N-type epitaxial layer, wherein the P-type drift region is spaced apart from the N-type well region;

a cathode electrode coupled to the second pad and including a first electrode and a first N-type doping region, wherein the first N-type doping region is electrically coupled to the first electrode, the first N-type doping region only is disposed in the N-type well region, and the first electrode is disposed on the N-type epitaxial layer;

an anode electrode coupled to the gate of the N-type LDMOS transistor and including a first P-type doping region, wherein the first P-type doping region is disposed in the P-type drift region; and

an isolation structure disposed in the P-type drift region, wherein the isolation structure is disposed between the N-type well region and the first P-type doping region,

wherein the first electrode of the cathode overlaps part of the isolation structure,

wherein the first electrode corresponds to a gate of a P-type LDMOS transistor,

wherein the N-type well region, the P-type drift region, the first P-type doping region and the isolation structure of the diode corresponds to an N-type well region, a P-type drift region, the drain electrode and an isolation structure of a P-type LDMOS transistor, respectively; and

a resistor having a first terminal that is coupled to the gate of the N-type LDMOS transistor and a second terminal that is coupled to the first pad.

9. The ESD protection circuit of claim 8 , further comprising:

an interlayer dielectric disposed on the first electrode and the N-type epitaxial layer,

a first vertical contact penetrating the interlayer dielectric layer and coupled to the first N-type doping region;

a second vertical contact spaced apart from the first vertical contact and penetrating the interlayer dielectric layer and coupled to the first N-type doping region;

a third vertical contact penetrating the interlayer dielectric layer and coupled to the first electrode;

a fourth vertical contact penetrating the interlayer dielectric layer and coupled to the first P-type doping region; and

a second electrode disposed on the interlayer dielectric layer and coupled to the first electrode, the first vertical contact, and the second vertical contact.

10. The ESD protection circuit of claim 8 , wherein the diode is configured to apply an induction voltage to the gate when a voltage lower than a breakdown voltage of the diode is applied to the ESD protection circuit, the induction voltage being determined by a capacitance between the cathode electrode and the anode electrode, and

wherein the diode is configured to apply a division voltage to the gate when a voltage higher than the breakdown voltage is applied to the ESD protection circuit, the division voltage being determined by a ratio of a resistance of the resistor and an on-state resistance of the diode.

11. The ESD protection circuit of claim 8 ,

wherein the N-type LDMOS transistor further includes a first P-type well region and an N-type drift region,

wherein the source electrode includes a second N-type doping region and a second P-type doping region, the second N-type doping region and the second P-type doping region being formed in the first P-type well region, and

wherein the drain electrode includes a third N-type doping region formed in the N-type drift region.

12. The ESD protection circuit of claim 11 ,

wherein the N-type epitaxial layer is disposed on a semiconductor substrate.

13. The ESD protection circuit of claim 12 ,

wherein an N-type buried layer is disposed in an upper portion of the semiconductor substrate, and

wherein the diode and the N-type LDMOS transistor are disposed on the N-type buried layer.

14. The ESD protection circuit of claim 12 ,

wherein an N-type buried layer is disposed in a first upper portion of the semiconductor substrate,

wherein a P-type buried layer is disposed in a second upper portion of the semiconductor substrate,

wherein the diode is disposed on the N-type buried layer, and

wherein the N-type LDMOS transistor is disposed on the P-type buried layer.

15. The ESD protection circuit of claim 11 ,

wherein a first dielectric layer disposed under the first electrode of the diode is thicker than a second dielectric layer disposed under the gate of the N-type LDMOS transistor.

16. The ESD protection circuit of claim 13 ,

wherein a deep trench is disposed in a boundary region between the diode and the N-type LDMOS transistor, and

wherein the deep trench penetrates the N-type buried layer.