Chip stack with electrically insulating walls
View Patent ↗A chip stack is provided and includes two or more chips, a solder joint operably disposed between adjacent ones of the two or more chips, the solder joint occupying about 25-30% or more of an area of the chip stack and insulating walls disposed on at least one of the two or more chips to separate the solder joint from an adjacent solder joint.
1. A system for forming chip stacks, comprising:
a chip stack element, comprising a substrate having two major surfaces, solder pads arrayed along a plane of one of the major surfaces with outer surfaces thereof disposed outwardly from a conductor and above insulators and walls formed of electrically insulating material disposed between adjacent ones of the solder pads; and
an adjacent chip stack element, comprising a substrate having two major surfaces and microbumps arrayed along a plane of one of the major surfaces with outer surfaces thereof disposed outwardly from a conductor and above insulators,
the adjacent chip stack element being disposable relative to the chip stack element such that solder joint material of the microbumps aligns with the solder pads of the chip stack element,
the adjacent chip stack element further comprising walls formed of electrically insulating material disposed between adjacent ones of the microbumps, top edge portions of the walls of the adjacent chip stack element being narrower than top edge portions of the walls of the chip stack element,
the walls of the chip stack element extending from uppermost surfaces of the insulators and being displaced from each of the adjacent ones of the solder pads, and
the walls of the adjacent chip stack element extending from uppermost surfaces of the insulators and contacting each of the adjacent ones of the microbumps.
2. The system according to claim 1 , wherein the walls of the chip stack element and the adjacent chip stack element comprise polymer.
3. The system according to claim 1 , wherein the solder pads occupy more than about 25-30% of an area of the one major surface.
4. The system according to claim 1 , wherein the solder pads occupy more than about 50% of an area of the one major surface.
5. The system according to claim 1 , wherein the solder pads have a pitch of about 100 microns or less.