IP Library › Granted Patent US 9,094,240
Granted Patent B2
US 9,094,240 · App. 14/257,254 · Granted Jul 28, 2015

Passive equalizer and high-speed digital signal transmission system using the same

Inventors: Eak Hwan Song (Seongnam-si, KR); Young Kun Kwon (Suwon-si, KR); Won Seob Kim (Seoul, KR); Hark Byeong Park (Hwaseong-si, KR); Hyun Sik Yun (Seoul, KR); Eun Seok Hong (Suwon-si, KR); Chul Soon Hwang (Suwon-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H04L27/01H04B3/144H04L25/03878
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Quick Facts
Patent No.
US 9,094,240
App. No.
14/257,254
Granted
Jul 28, 2015
Kind
B2
Abstract

Disclosed herein are a passive equalizer and a high-speed digital signal transmission system, including first and second impedances connected in series to a first transfer line, third and fourth impedances connected in series to a second transfer line, a first inductor connected in parallel between the first impedance and the second impedance, a second inductor connected in parallel between the third impedance and the fourth impedance, and a resistor connected in series between the first inductor and the second inductor.

Claims (244)

1. A passive equalizer comprising:

first and second impedances connected in series to a transfer line;

an inductor connected in parallel between the first impedance and the second impedance;

a resistor connected in series to the inductor; and

a ground connected in series to the resistor,

wherein a transfer function (TF) as transfer characteristics of the passive equalizer is calculated according to Expression 1 below:

TF

=

K

⁡

(

1

+

s

/

s

1

1

+

s

/

s

2

)

(

1

)

where K is

2

⁢

⁢

R

Z

0

+

2

⁢

⁢

R

,

S 1 is R/L, and S 2 is

Z

0

+

2

⁢

⁢

R

2

⁢

⁢

L

and where Z o is an impedance of a transfer line, R is a resistance, L is an inductance, and S, S1, and S2 are a first, second, and third frequency, respectively.

2. The passive equalizer according to claim 1 , wherein the first impedance is connected to an input terminal and the second impedance is connected to an output terminal.

3. A passive equalizer comprising:

first and second impedances connected in series to a first transfer line;

third and fourth impedances connected in series to a second transfer line;

a first inductor connected in parallel between the first impedance and the second impedance;

a second inductor connected in parallel between the third impedance and the fourth impedance; and

a resistor connected in series between the first inductor and the second inductor,

wherein a transfer function (TF) as transfer characteristics of the passive equalizer is calculated according to Expression 1 below:

TF

=

K

⁡

(

1

+

s

/

s

1

1

+

s

/

s

2

)

(

1

)

where K is

2

⁢

⁢

R

Z

0

+

2

⁢

⁢

R

,

S 1 is R/L, and S 2 is

Z

0

+

2

⁢

⁢

R

2

⁢

⁢

L

and where Z o is an impedance of a transfer line, R is a resistance, L is an inductance, and S, S1, and S2 are a first, second, and third frequency, respectively.

4. The passive equalizer according to claim 3 , wherein the first impedance is connected to an input terminal and the second impedance is connected to an output terminal.

5. The passive equalizer according to claim 3 , wherein the third impedance is connected to an input terminal and the fourth impedance is connected to an output terminal.

6. A high-speed digital signal transmission system comprising:

a transmitter to transmit a first signal;

a receiver to receive a second signal and to output the second signal;

a channel, formed between the transmitter and the receiver, to convey the first signal transmitted from the transmitter; and

a passive equalizer formed between the transmitter and the receiver, to compensate for a frequency of a third signal received through an input terminal along a transfer line and to equalize transfer characteristics of the third signal up to a maximum frequency,

wherein a transfer function (TF) as transfer characteristics of the passive equalizer is calculated according to Expression 1 below:

TF

=

K

⁡

(

1

+

s

/

s

1

1

+

s

/

s

2

)

(

1

)

where K is

2

⁢

⁢

R

Z

0

+

2

⁢

⁢

R

,

S 1 is R/L, and S 2 is

Z

0

+

2

⁢

⁢

R

2

⁢

⁢

L

and where Z o is an impedance of a transfer line, R is a resistance, L is an inductance, and S, S1, and S2 are a first, second, and third frequency, respectively.

7. The high-speed digital signal transmission system according to claim 6 , wherein the passive equalizer includes a single-ended line as the transfer line and comprises:

first and second impedances connected in series to the transfer line;

an inductor connected in parallel between the first impedance and the second impedance;

a resistor connected in series to the inductor; and

a ground connected in series to the resistor.

8. The high-speed digital signal transmission system according to claim 6 , wherein the passive equalizer includes differential lines as the transfer line and comprises:

first and second impedances connected in series to a first transfer line;

third and fourth impedances connected in series to a second transfer line;

a first inductor connected in parallel between the first impedance and the second impedance;

a second inductor connected in parallel between the third impedance and the fourth impedance; and

a resistor connected in series between the first inductor and the second inductor.

9. The high-speed digital signal transmission system according to claim 6 , wherein the passive equalizer is formed between the transmitter and the channel.

10. The high-speed digital signal transmission system according to claim 6 , wherein the passive equalizer is formed between the channel and the receiver.

11. The high-speed digital signal transmission system according to claim 6 , wherein the channel comprises a first channel and a second channel, and

wherein the passive equalizer is formed between the first channel and the second channel.

12. The high-speed digital signal transmission system according to claim 6 , wherein the passive equalizer comprises a first passive equalizer and a second passive equalizer,

wherein the first passive equalizer is formed between the transmitter and the channel, and

wherein the second passive equalizer is formed between the channel and the receiver.

13. The high-speed digital signal transmission system according to claim 6 , further comprising an active device formed between the transmitter and the receiver.

14. A high-speed digital signal transmission system comprising:

a transmitter to transmit the high-speed digital signal;

a receiver to receive the high-speed digital signal and to output the received signal; and

a passive equalizer formed between the transmitter and the receiver to equalize transfer characteristics of the high-speed digital signal up to a maximum frequency,

wherein a transfer function (TF) as transfer characteristics of the passive equalizer is calculated according to Expression 1 below:

TF

=

K

⁡

(

1

+

s

/

s

1

1

+

s

/

s

2

)

(

1

)

where K is

2

⁢

R

Z

0

+

2

⁢

R

,

S 1 is R/L, and S 2 is

Z

0

+

2

⁢

⁢

R

2

⁢

⁢

L

and where Z o is an impedance of a transfer line, R is a resistance, L is an inductance, and S, S1, and S2 are a first, second, and third frequency, respectively.

15. The high-speed digital signal transmission system according to claim 14 , wherein the passive equalizer is configured to compensate for frequency-dependent attenuation of the high-speed digital signal, which is received along a transfer line.

16. The high-speed digital signal transmission system according to claim 14 , wherein the passive equalizer includes a single-ended line as the transfer line and comprises:

first and second impedances connected in series to a transfer line;

an inductor connected in parallel between the first impedance and the second impedance;

a resistor connected in series to the inductor; and

a ground connected in series to the resistor.

17. The high-speed digital signal transmission system according to claim 14 , wherein the passive equalizer includes differential lines as the transfer line and comprises:

first and second impedances connected in series to a first transfer line;

third and fourth impedances connected in series to a second transfer line;

a first inductor connected in parallel between the first impedance and the second impedance;

a second inductor connected in parallel between the third impedance and the fourth impedance; and

a resistor connected in series between the first inductor and the second inductor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 27, 2014
From: SONG, EAK HWAN; KWON, YOUNG KUN; KIM, WON SEOB; PARK, HARK BYEONG; YUN, HYUN SIK; HONG, EUN SEOK; HWANG, CHUL SOON
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 033193/0796 →
Priority Claims (1)
KR 10-2013-0043426 · Apr 19, 2013 · national
Continuity (1)
Related Publication 20140314136A1 · Oct 23, 2014