IP Library Granted Patent US 9,098,921
Granted Patent B2
US 9,098,921 · App. 13/722,516 · Granted Aug 4, 2015

Image processor and image processing method

Inventors: Soichiro Kurokawa (Kanagawa, JP); Toshiyuki Nagatsuma (Kanagawa, JP); Tsutomu Harada (Kanagawa, JP)
Assignee: Japan Display Inc.
G06T5/40H04N5/20H04N5/202
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Quick Facts
Patent No.
US 9,098,921
App. No.
13/722,516
Granted
Aug 4, 2015
Kind
B2
Abstract

Disclosed herein is an image processor including: a random number sequence generation section adapted to generate a random number sequence; a random number-superimposed luminance variable generation section adapted to generate a random number-superimposed luminance variable by superimposing the random number sequence on a luminance variable; and a random number-superimposed image signal generation section adapted to generate a random number-superimposed image signal by superimposing the random number-superimposed luminance variable on an image signal.

Claims (28)

1. An image processor, comprising:

a random number sequence generation section adapted to generate a random number sequence;

a random number-superimposed luminance variable generation section adapted to generate a random number-superimposed luminance variable by superimposing the random number sequence on a luminance variable; and

a random number-superimposed image signal generation section adapted to generate a random number-superimposed image signal by superimposing the random number-superimposed luminance variable on an image signal,

wherein the random number sequence generation section inverts the polarity of the random number sequence once every two frames without changing the absolute values thereof.

2. An image processor of, comprising:

a random number sequence generation section adapted to generate a random number sequence;

a random number-superimposed luminance variable generation section adapted to generate a random number-superimposed luminance variable by superimposing the random number sequence on a luminance variable; and

a random number-superimposed image signal generation section adapted to generate a random number-superimposed image signal by superimposing the random number-superimposed luminance variable on an image signal,

wherein the random number-superimposed image signal generation section performs rounding adapted to round the random number-superimposed image signal to a predetermined number of bits and outputs the resultant signal.

3. The image processor of claim 2 , wherein

the random number-superimposed image signal generation section rounds the random number-superimposed image signal and outputs an image with the dithered lowest bit.

4. A non-transitory computer-readable medium having thereon instructions which, when executed by a processing unit, causes the processing unit to perform operations comprising:

generating, by the processing unit, a random number sequence;

generating, by the processing unit, a random number-superimposed luminance variable by superimposing the random number sequence on a luminance variable;

generating, by the processing unit, a random number-superimposed image signal by superimposing the random number-superimposed luminance variable on an image signal; and

inverting, by the processing unit, the polarity of the random number sequence once every two frames without changing the absolute values thereof.

5. A non-transitory computer-readable medium having thereon instructions which, when executed by a processing unit, causes the processing unit to perform operations comprising:

generating, by the processing unit, a random number sequence;

generating, by the processing unit, a random number-superimposed luminance variable by superimposing the random number sequence on a luminance variable;

generating, by the processing unit, a random number-superimposed image signal by superimposing the random number-superimposed luminance variable on an image signal; and

performing, by the processing unit, rounding adapted to round the random number-superimposed image signal to a predetermined number of bits and outputting the resultant signal.

6. The image processing method of claim 5 comprising:

rounding, by the processing unit, the random number-superimposed image signal and outputting an image with the dithered lowest bit.

7. The image processor of claim 2 , wherein

the random number sequence generation section generates and outputs a random number sequence having the same set of numbers every frame.

8. The non-transitory computer-readable medium of claim 5 , the operations further comprising:

generating and outputting, by the processing unit, a random number sequence having the same set of numbers every frame.

Assignments (2)
CHANGE OF NAME Recorded Jun 23, 2015
From: JAPAN DISPLAY WEST INC.
To: JAPAN DISPLAY INC.
Reel/Frame 036009/0475 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 8, 2013
From: KUROKAWA, SOICHIRO; NAGATSUMA, TOSHIYUKI; HARADA, TSUTOMU
To: JAPAN DISPLAY WEST INC.
Reel/Frame 029589/0107 →
Priority Claims (1)
JP 2012-063752 · Mar 21, 2012 · national
Continuity (1)
Related Publication 20130251285A1 · Sep 26, 2013