Semiconductor device and method of forming junction enhanced trench power MOSFET
A semiconductor device has a substrate and first and second gate structures formed over a first surface of the substrate. A drain region is formed in the substrate as a second surface of the substrate. An epitaxial region is formed in the substrate over the drain region. A sidewall spacer is formed over the first and second gate structures. A lateral LDD region is formed between the first and second gate structures. A trench is formed through the lateral LDD region and partially through the substrate self-aligned to the sidewall spacer. A vertical drift region is formed along a sidewall of the trench. An insulating material is deposited in the trench. A first source region is formed adjacent to the first gate structure opposite the lateral LDD region. A second source region is formed adjacent to the second gate structure opposite the lateral LDD region.
1. A method of making a semiconductor device, comprising:
providing a substrate;
forming a gate structure over a first surface of the substrate;
forming a lateral drift region adjacent to the gate structure;
forming a sidewall spacer over the gate structure;
forming a trench through the lateral drift region and partially through the substrate, the trench self-aligned to the sidewall spacer;
forming a vertical drift region along a sidewall of the trench;
depositing an insulating material in the trench; and
forming a source region adjacent to the gate structure opposite the lateral drift region.
2. The method of claim 1 , wherein providing the substrate includes:
forming a drain region in the substrate as a second surface of the substrate opposite the first surface of the substrate; and
forming an epitaxial region in the substrate over the drain region.
3. The method of claim 2 , further including:
forming an insulating layer over the first surface of the substrate and the gate structure;
forming a first conductive layer over the insulating layer electrically connected to the source region; and
forming a second conductive layer over the second surface of the substrate electrically connected to the drain region.
4. The method of claim 1 , further including forming a channel region adjacent to the gate structure opposite the lateral drift region.
5. The method of claim 1 , further including forming a vertical column region adjacent to the vertical drift region.
6. The method of claim 1 , further including forming a conductive plug in the trench.
7. A method of making a semiconductor device, comprising:
providing a substrate;
forming a gate structure over a first surface of the substrate;
forming a lateral drift region adjacent to the gate structure;
forming a sidewall spacer over the gate structure for self-aligning the insulating trench;
forming an insulating trench through the lateral drift region and partially through the substrate;
forming a vertical drift region partially through the substrate and contacting the lateral drift region; and
forming a source region adjacent to the gate structure opposite the lateral drift region.
8. The method of claim 7 , further including forming the vertical drift region along a sidewall of the trench.
9. The method of claim 8 , wherein forming the vertical drift region includes forming a plurality of doped regions between the lateral drift region and source region.
10. The method of claim 7 , wherein providing the substrate includes:
forming a drain region in the substrate as a second surface of the substrate opposite the first surface of the substrate; and
forming an epitaxial region in the substrate over the drain region.
11. The method of claim 10 , further including:
forming an insulating layer over the first surface of the substrate and the gate structure;
forming a first conductive layer over the insulating layer electrically connected to the source region; and
forming a second conductive layer over the second surface of the substrate electrically connected to the drain region.
12. A semiconductor device, comprising:
a substrate;
a gate structure formed over a first surface of the substrate;
a lateral drift region formed adjacent to the gate structure;
a sidewall spacer formed over the gate structure for self-aligning the insulating trench;
an insulating trench formed through the lateral drift region and partially through the substrate;
a vertical drift region formed partially through the substrate and contacting the lateral drift region; and
a source region formed adjacent to the gate structure opposite the lateral drift region.
13. The semiconductor device of claim 12 , further including a conductive plug formed in the insulating trench.
14. The semiconductor device of claim 12 , wherein the substrate includes:
a drain region formed in the substrate as a second surface of the substrate opposite the first surface of the substrate; and
an epitaxial region formed in the substrate over the drain region.
15. The semiconductor device of claim 12 , further including a vertical column region formed adjacent to the vertical drift region.
16. A semiconductor device, comprising:
a substrate;
a gate structure formed over a first surface of the substrate;
a lateral drift region formed adjacent to the gate structure;
a sidewall spacer formed over the gate structure;
a trench formed through the lateral drift region and partially through the substrate, the trench self-aligned to the sidewall spacer;
a vertical drift region formed along a sidewall of the trench;
an insulating material deposited in the trench; and
a source region formed adjacent to the gate structure opposite the lateral drift region.
17. The semiconductor device of claim 16 , further including a vertical column region formed adjacent to the vertical drift region.
18. The semiconductor device of claim 16 , further including a conductive plug formed in the trench.
19. The semiconductor device of claim 16 , wherein the substrate includes:
a drain region formed in the substrate as a second surface of the substrate opposite the first surface of the substrate; and
an epitaxial region formed in the substrate over the drain region.
20. The semiconductor device of claim 19 , further including:
an insulating layer formed over the first surface of the substrate and the gate structure;
a first conductive layer formed over the insulating layer electrically connected to the source region; and
a second conductive layer formed over the second surface of the substrate electrically connected to the drain region.
21. The semiconductor device of claim 16 , further including a channel region formed adjacent to the gate structure opposite the lateral drift region.