Successive approximation register analog-to-digital converter and associated control method
The present invention provides a successive approximation register analog-to-digital converter (SAR ADC), where a high bit capacitor of the SAR ADC is composed of a plurality of sub-capacitors, and these sub-capacitors are calibrated when the SAR ADC is working. Therefore, the working speed of the SAR ADC will not be influenced. In addition, a capacitance of each sub-capacitor is lower than a redundant capacitance of the SAR ADC, therefore, input signals of the SAR ADC are allowed to have full swing.
1. A successive approximation register analog-to-digital converter (SAR ADC), comprising:
a first bit capacitor array, for receiving a first input signal, wherein the first bit capacitor array comprises a plurality of first bit capacitors, and at least one of high first bit capacitors is composed of a plurality of sub-capacitors, and each sub-capacitor is selectively connected to a first reference voltage, a second reference voltage or a common voltage via its corresponding switch;
a second bit capacitor array, for receiving a second input signal, wherein the second bit capacitor array includes a plurality of second bit capacitors, and at least one of high second bit capacitors is composed of a plurality of sub-capacitors, and each sub-capacitor is selectively connected to the first reference voltage, the second reference voltage or the common voltage via its corresponding switch;
a comparator, coupled to the first bit capacitor array and the second bit capacitor array, for comparing outputs of the first bit capacitor array and the second bit capacitor array to generate a comparison signal; and
a processing circuit, coupled to the comparator, for controlling capacitor-switching operations of the first bit capacitor array and the second bit capacitor array to generate a digital output of the SAR ADC;
wherein during a period that the SAR ADC receives the first input signal and the second input signal to generate the digital output, the processing circuit calibrates the sub-capacitors of at least one of the high first bit capacitors of the first bit capacitor array to generate a plurality of weight values of the sub-capacitors, and the processing circuit determines a weight value of the at least one of the high first bit capacitors of the first bit capacitor array according to the weight values of the sub-capacitors; and the processing circuit calibrates the sub-capacitors of at least one of the high second bit capacitors of the second bit capacitor array to generate a plurality of weight values of the sub-capacitors, and the processing circuit determines a weight value of the at least one of the high second bit capacitors of the second bit capacitor array according to the weight values of the sub-capacitors.
2. The SAR ADC of claim 1 , wherein capacitances of all the sub-capacitors of the one of the high first bit capacitors of the first bit capacitor array are the same.
3. The SAR ADC of claim 1 , wherein the SAR ADC is an N-bit SAR ADC, the first bit capacitors are not binary weighted capacitors; and for each first bit capacitor, its capacitance is not greater than a summation of capacitances of all the lower bit capacitors, and a summation of capacitances of a unit capacitor and all the first bit capacitors is not lower than 2 (N-1) times a capacitance of a least first bit capacitor.
4. The SAR ADC of claim 3 , wherein in the first bit capacitor array, any first bit capacitor whose capacitance is greater than a redundant capacitance is composed of a plurality of sub-capacitors, and a capacitance of each sub-capacitor is less than the redundant capacitance, where the redundant capacitance is a difference between the summation of the capacitances of the unit capacitor and all the first bit capacitors with 2 (N-1) times the capacitance of the least bit capacitor.
5. The SAR ADC of claim 4 , wherein during a period that the SAR ADC receives the first input signal and the second input signal to generate the digital output, the processing circuit calibrates the sub-capacitors of at least one of the high first bit capacitors of the first bit capacitor array to generate a plurality of weight values of the sub-capacitors, and the processing circuit determines a weight value of the at least one of the high first bit capacitors of the first bit capacitor array according to the weight values of the sub-capacitors; and the processing circuit calibrates the sub-capacitors of at least one of the high second bit capacitors of the second bit capacitor array to generate a plurality of weight values of the sub-capacitors, and the processing circuit determines a weight value of the at least one of the high second bit capacitors of the second bit capacitor array according to the weight values of the sub-capacitors.
6. The SAR ADC of claim 1 , wherein the SAR ADC allows the first input signal and the second input signal to have full swing.
7. A method for controlling a successive approximation register analog-to-digital converter (SAR ADC), wherein the SAR ADC comprises:
a first bit capacitor array, for receiving a first input signal, wherein the first bit capacitor array comprises a plurality of first bit capacitors, and at least one of high first bit capacitors is composed of a plurality of sub-capacitors, and each sub-capacitor is selectively connected to a first reference voltage, a second reference voltage or a common voltage via its corresponding switch; and
a second bit capacitor array, for receiving a second input signal, wherein the second bit capacitor array includes a plurality of second bit capacitors, and at least one of high second bit capacitors is composed of a plurality of sub-capacitors, and each sub-capacitor is selectively connected to the first reference voltage, the second reference voltage or the common voltage via its corresponding switch; and
the method comprises:
comparing outputs of the first bit capacitor array and the second bit capacitor array to generate a comparison signal;
determining weight values of each first bit capacitors or each second bit capacitors according to the comparison signal;
generating a digital output of the SAR ADC according to the comparison signal and the determined weight values;
during a period that the SAR ADC receives the first input signal and the second input signal to generate the digital output, calibrating the sub-capacitors of at least one of the high first bit capacitors of the first bit capacitor array to generate a plurality of weight values of the sub-capacitors, and determining a weight value of the at least one of the high first bit capacitors of the first bit capacitor array according to the weight values of the sub-capacitors; and
calibrating the sub-capacitors of at least one of the high second bit capacitors of the second bit capacitor array to generate a plurality of weight values of the sub-capacitors, and the determining a weight value of the at least one of the high second bit capacitors of the second bit capacitor array according to the weight values of the sub-capacitors.
8. The method of claim 7 , wherein capacitances of all the sub-capacitors of the one of the high first bit capacitors of the first bit capacitor array are the same.
9. The method of claim 7 , wherein the SAR ADC is an N-bit SAR ADC, the first bit capacitors are not binary weighted capacitors; and for each first bit capacitor, its capacitance is not greater than a summation of capacitances of all the lower bit capacitors, and a summation of capacitances of a unit capacitor and all the first bit capacitors is not lower than 2 (N-1) times a capacitance of a least first bit capacitor.
10. The method of claim 9 , wherein in the first bit capacitor array, any first bit capacitor whose capacitance is greater than a redundant capacitance is composed of a plurality of sub-capacitors, and a capacitance of each sub-capacitor is less than the redundant capacitance, where the redundant capacitance is a difference between the summation of the capacitances of the unit capacitor and all the first bit capacitors with 2 (N-1) times the capacitance of the least bit capacitor.
11. The method of claim 7 , wherein each of the first input signal and the second input signal is allowed to have full swing.
12. A successive approximation register analog-to-digital converter (SAR ADC), comprising:
a first bit capacitor array, for receiving a first input signal, wherein the first bit capacitor array comprises a plurality of first bit capacitors, and at least one of high first bit capacitors is composed of a plurality of sub-capacitors;
a second bit capacitor array, for receiving a second input signal, wherein the second bit capacitor array includes a plurality of second bit capacitors, and at least one of high second bit capacitors is composed of a plurality of sub-capacitors;
a comparator, coupled to the first bit capacitor array and the second bit capacitor array, for comparing outputs of the first bit capacitor array and the second bit capacitor array to generate a comparison signal; and
a processing circuit, coupled to the comparator, for controlling capacitor-switching operations of the first bit capacitor array and the second bit capacitor array to generate an N-bit digital output of the SAR ADC;
wherein in the first bit capacitor array, any first bit capacitor whose capacitance is greater than a redundant capacitance is composed of a plurality of sub-capacitors, and a capacitance of each sub-capacitor is less than the redundant capacitance, where the redundant capacitance is a difference between a summation of capacitances of a unit capacitor and all the first bit capacitors with 2 (N-1) times a capacitance of a least bit capacitor.
13. The SAR ADC of claim 12 , wherein the first bit capacitors are not binary weighted capacitors; and for each first bit capacitor, its capacitance is not greater than a summation of capacitances of all the lower bit capacitors, and the summation of the capacitances of the unit capacitor and all the first bit capacitors is not lower than 2 (N-1) times the capacitance of the least first bit capacitor.