Circuit and method for monolithic stacked integrated circuit testing

1. A monolithic stacked integrated circuit (IC) comprising a known-good-layer (KGL) test circuit that includes a scan segment in a first layer of the IC, wherein the first layer is an upper layer of the IC, the KGL test circuit comprising:

a first test input, coupled to an input of the scan segment, to receive a first scan shift data;

a first multiplexer, the first multiplexer having a first data input, a second data input, a first selection input, and a first data output wherein the first data input is coupled to the first test input and the second data input is coupled to an output of the scan segment;

a first test output, coupled to the first data output, to send a second scan shift data to a second layer;

a second test input, to receive a third scan shift data from the second layer;

a second multiplexer, the second multiplexer having a third data input, a fourth data input, a second selection input, and a second data output wherein the third data input is coupled to the second test input and the fourth data input is coupled to the first data output;

a second test output, coupled to the second data output, to send a fourth scan shift data;

a first control element, coupled to the first selection input; and

a second control element, coupled to the second selection input.

2. The IC of claim 1 , wherein:

the first control element is: an input to the first layer or a programmable register in the first layer; and

the second control element is: another input to the first layer or another programmable register in the first layer.

3. The IC of claim 1 , wherein the control elements are registers programmed using one of:

a second scan chain, the second scan chain having the control elements;

an IEEE 1149.1 interface; and

an IEEE 1500 interface.

4. The IC of claim 1 , wherein:

the second layer is one of: a base layer of the IC and another upper layer of the IC; and

the first layer is over the second layer.

5. The IC of claim 1 , wherein the scan segment is register-based.

6. The IC of claim 1 , wherein:

the first control element is a fixed value thereby the first control element and the first multiplexer are degenerated; and

the first test output and the fourth data input are coupled to the output of the scan segment.

7. The IC of claim 1 , wherein:

the control elements are fixed values thereby the control elements and the multiplexers are degenerated; and

the second test output is coupled to the output of the scan segment.

8. A method for generating a monolithic stacked integrated circuit (IC) known-good-layer (KGL) test pattern, the method comprising:

receiving a circuit design of the IC, wherein:

the circuit design includes a first layer, a second layer and a scan chain;

the scan chain includes a first scan segment in the first layer and a second

scan segment in the second layer;

the second layer includes:

a first test input, coupled to an input of the second scan segment;

a first multiplexer, the first multiplexer having a first data input, a second data input, a first selection input and a first data output wherein the first data input is coupled to the first test input and the second data input is coupled to an output of the second scan segment;

a first test output, coupled to the first data output;

a second test input;

a second multiplexer, the second multiplexer having a third data input, a fourth data input, a second selection input and a second data output wherein the third data input is coupled to the second test input and the fourth data input is coupled to the first data output; and

a second test output, coupled to the second data output;

the first layer includes a third test input coupled to an input of the first scan segment, a third test output, and a means for coupling the third test output to an output of the first scan segment; and

the circuit design further includes a means for coupling the first test output to the third test input and a means for coupling the third test output to the second test input;

configuring the third test input as a scan input;

configuring the third test output as a scan output;

generating test patterns for detecting faults at the first layer;

configuring the first test input as another scan input;

configuring the second test output as another scan output; and

generating test patterns for detecting faults at the second layer.

9. The method of claim 8 , further comprising, before the generating the test patterns for detecting faults at the second layer:

configuring the first selection input thereby passing to the first data output one of: the first data input and the second data input; and

configuring the second selection input thereby passing to the second data output one of:

the third data input and the fourth data input.

10. The method of claim 9 , wherein the configuring the first and the second selection inputs uses one of:

inputs at the second layer;

a second scan chain, the second scan chain having a plurality of scan flip-flops at the second layer;

an IEEE 1149.1 interface at the second layer; and

an IEEE 1500 interface at the second layer.

11. The method of claim 8 , wherein:

the first layer is one of: a base layer of the IC or an upper layer of the IC;

the second layer is another upper layer of the IC; and

the second layer is over the first layer.

12. A monolithic stacked integrated circuit (IC) known-good-layer (KGL) fault testing method, comprising:

receiving a base layer of the IC, the base layer having a substrate, a first surface, and a second surface;

attaching a first plurality of probe pads to the first surface, the first plurality of probe pads electrically contacting the base layer;

applying a first fault testing through the first plurality of probe pads;

forming an insulation layer over the base layer;

forming an upper layer of the IC over the insulation layer, wherein the upper layer has a third surface and a fourth surface, the third surface is over the insulation layer, and the upper layer electrically contacts the base layer;

attaching a second plurality of probe pads to the fourth surface, the second plurality of probe pads electrically contacting the upper layer; and

applying a second fault testing through the second plurality of probe pads.

13. The IC testing method in claim 12 , further comprising, detaching the first plurality of probe pads before the forming the insulation layer over the base layer.

14. The IC testing method in claim 12 , wherein the forming the insulation layer over the base layer includes:

depositing a dielectric material layer over the base layer; and

performing a polishing process to the dielectric material layer.

15. The IC testing method in claim 12 , wherein the substrate includes silicon.

16. The IC testing method in claim 12 , wherein the first surface is a surface of the substrate.

17. The IC testing method in claim 12 , wherein the upper layer electrically contacts the base layer using vias through the third surface, the insulation layer, and the second surface.

18. The IC testing method in claim 12 , wherein:

the IC includes KGL test circuits in at least the upper layer; and

the first and the second fault testing use KGL test patterns.

19. The IC of claim 1 , wherein:

the IC includes a third layer;

the second layer is over the third layer;

the first layer is over the second layer; and

the KGL test circuit includes a scan chain that go through the first, second, and third layers.

20. The method of claim 8 , further comprising:

generating test patterns for detecting faults at both the first and second layers.