Memory device with tracking wordline voltage level circuit and method

1. A memory comprising:

a clock generator for providing a first clock signal responsive to a second clock signal and a feedback signal;

a memory array having a plurality of memory cells accessed using the first clock signal; and

a tracking circuit, the tracking circuit comprising:

a feedback loop for providing the feedback signal, the feedback loop comprising a tracking wordline, a tracking bitline, a tracking bit cell, and a tracking wordline driver providing a tracking wordline signal for driving the tracking wordline responsive to the first clock signal; and

a tracking wordline level tuner, the tracking wordline level tuner setting a voltage level of the tracking wordline signal on the tracking wordline to one of at least two voltage levels dependent on a state of a weak bit control signal indicative of the presence of a weak memory cell in the memory array.

2. The memory of claim 1 , wherein the tracking wordline level tuner comprises a voltage divider coupled to the tracking wordline driver.

3. The memory of claim 2 , wherein the voltage divider comprises one or more pulldown transistors coupled to a supply node of the tracking wordline driver, the pulldown transistors under control of the weak bit control signal.

4. The memory of claim 3 , wherein the voltage divider further comprises a transistor coupled between a high power supply node and the supply node of the tracking wordline driver.

5. The memory of claim 4 , wherein the transistor is a PMOS transistor having its gate terminal coupled to a low power supply node or a NMOS transistor having its gate terminal coupled to a high power supply node.

6. The memory of claim 2 , wherein the tracking wordline level tuner comprises a voltage level suppressor coupled to the tracking wordline.

7. The memory of claim 6 , wherein the voltage suppressor comprises one or more pulldovvn transistors coupled to the tracking wordline, the pulldown transistors under control of the weak bit control signal.

8. The memory of claim 7 , wherein the pulldown transistors are selected from the group consisting of PMOS transistors, NMOS transistors or a mix of NMOS and PMOS transistors.

9. The memory of claim 1 , wherein the tracking wordline level tuner is controllable to set the voltage level of the tracking wordline signal to at least two different reduced voltage levels, the at least two different voltage levels corresponding to different levels of weak bit potentially present in the memory array.

10. The memory of claim 1 , further comprising wherein the memory array is part of a SRAM macro.

11. A memory comprising:

a SRAM macro, the SRAM macro using a first clock signal in accessing SRAM memory cells;

an internal clock generator for providing the first clock signal responsive to a second clock signal and a feedback signal;

a feedback loop for providing the feedback signal, the feedback loop comprising a tracking wordline, a tracking bitline, a tracking bit cell coupled between the tracking wordline and the tracking bitline, a tracking wordline driver providing a tracking wordline signal for driving the tracking wordline responsive to the first clock signal; and

a tracking wordline level tuner, the tracking wordline level tuner setting a voltage level of the tracking wordline signal on the tracking wordline to one of a high driving voltage level or a suppressed driving voltage level dependent on a state of a weak bit control signal indicative of the presence of a weak memory cell in the SRAM macro.

12. The memory of claim 11 , wherein the tracking wordline level tuner comprises a voltage divider coupled to the tracking wordline driver.

13. The memory of claim 12 , wherein the voltage divider comprises one or more pulldown transistors coupled to a supply node of the tracking wordline driver, the pulldown transistors under control of the weak bit control signal.

14. The memory of claim 13 , wherein the voltage divider further comprises a transistor coupled between a high power supply node and the supply node of the tracking wordline driver, wherein the transistor is a PMOS transistor having its gate terminal coupled to a low power supply node or a NMOS transistor having its gate terminal coupled to a high power supply node.

15. The memory of claim 12 , wherein the voltage divider is controllable to provide at least two different suppressed driving voltage levels, the at least two different suppressed driving voltage levels corresponding to different levels of weak bit potentially present in the SRAM macro.

16. The memory of claim 11 , wherein the tracking wordline level tuner comprises a voltage level suppressor coupled to the tracking wordline.

17. The memory of claim 16 , wherein the voltage suppressor comprises one or more pulldown transistors coupled to the tracking wordline, the pulldown transistors under control of the weak bit control signal.

18. The memory of claim 16 , wherein the voltage level suppressor is controllable to provide at least two different suppressed driving voltage levels, the at least two different suppressed driving voltage levels corresponding to different levels of weak bit potentially present in the SRAM macro.

19. A method of providing an internal clock signal for a memory using tracking, comprising the steps of:

receiving a weak bit control signal indicative of the presence of a weak memory cell in a memory array;

if the weak bit control signal is in a first logic state indicating no weak memory cell, driving a tracking wordline of a tracking feedback loop to a first voltage level;

if the weak bit control signal is in a second logic state indicating the weak memory cell is present, driving the tracking wordline to a second voltage level, the second voltage level being less than said first voltage level;

tracking a bit cell current from a tracking bitline coupled to the tracking wordline; and

controlling a pulse width of the internal clock signal based on said tracking.

20. The method of claim 19 , further comprising the steps of accessing a memory cell using the internal clock signal.